From patchwork Mon Feb 26 14:28:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 86388 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 997F13858285 for ; Mon, 26 Feb 2024 14:29:39 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id 395403858CDB for ; Mon, 26 Feb 2024 14:29:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 395403858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 395403858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957746; cv=none; b=VAMYltyjEcLFvh88NsaLpITqGHbP+0VmOKgjelQrmL6umFv2+6bWAXRJsm+dxKhSUv8zN4FU7Yb+fNxDb7hC/tWkihgTZyG/GUkp0FXs604CyrMfCKn+yPwA+sB672yI5blHLrPIlHKELtzYm2by6RjoGpYe+vSNdmryZ83odhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957746; c=relaxed/simple; bh=Y70M3kbHuuu4GyWuOktZyyO6WeY+s5pSJqeNjBN85xk=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=AykVtWnLNedp/TDcFOyV2/V6ZpVOOp5qqdfuQOGJ8bXALBMMCVW1JdUO7QouhIi0kRKZxZgD3u8SQEh+EwgVFWBcqJ31X53DrPsi/crd4QRctNTuIUy5qMz4xOs49Kaj1r11FK88pAgSHxSG+REb0uzgdIB6+x4TxmnAeyONvNU= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q8K02m021970; Mon, 26 Feb 2024 14:28:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=SABZYEzUWg4k4jEWV8rlRD6iDjpnuBpZJO7xDIjHMbc=; b=qjP 2ib6pNjpqzLsPh1bWfFN9wHluiReghEwuvCiSUWfRH0nVncS7TKAa2CLfLAjFsBm tQSeaqZ2p9caia7EX9xhHAFcKafz3y9c2rFOQhzZh5OF+BwW/+xi4OEWiueqt+Ed cp0Td9IaLuor+lVkYkrTuwAN4WT2xsUZuWcedKSMick+mDDPxe5h1o7TBnOSJXba M9pt664RAl/AQ1pgiEDHjHzhdQ/2oXyuqY1VFYu/E0fo2VuiWNocwoU8WwdFSU7m VkhygMYhcsB6Ri+cNpHn6kF+hUCgXPx4U5KvtDw4cfxTBolGcdQxp7Fj1+69lnIM t38EwPXyOistKmJus+A== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr7v-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:28:57 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:28:57 +0000 From: To: CC: , , , Bhushan Attarde Subject: [PATCH 10/11] sim: riscv: Add double precision floating-point basic arithmetic instructions Date: Mon, 26 Feb 2024 14:28:44 +0000 Message-ID: <20240226142845.1629113-2-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226142845.1629113-1-bhushan.attarde@imgtec.com> References: <20240226142845.1629113-1-bhushan.attarde@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: iSfXkAahJZRy7d1xum1HM1xW6m-lkPru X-Proofpoint-ORIG-GUID: iSfXkAahJZRy7d1xum1HM1xW6m-lkPru X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Bhushan Attarde Added simulation of following single precision floating-point instructions fadd.d, fsub.d, fmul.d, fdiv.d and fsqrt.d. Update test file sim/testsuite/riscv/d-basic-arith.s to test these instructions. --- sim/riscv/sim-main.c | 45 ++++++++++++++++++++++++++ sim/testsuite/riscv/d-basic-arith.s | 50 +++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 4a102df74e0..e715ca2501e 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1421,6 +1421,31 @@ float64_math (SIM_CPU *cpu, int rd, int rs1, int rs2, int rs3, int rm, frd_name, frs1_name, frs2_name, frs3_name, rm); result = -((a * b) + c); break; + case FADD: + TRACE_INSN (cpu, "fadd.d %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a + b; + break; + case FSUB: + TRACE_INSN (cpu, "fsub.d %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a - b; + break; + case FMUL: + TRACE_INSN (cpu, "fmul.d %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a * b; + break; + case FDIV: + TRACE_INSN (cpu, "fdiv.d %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a / b; + break; + case FSQRT: + TRACE_INSN (cpu, "fsqrt.d %s, %s, rm=%d;", + frd_name, frs1_name, rm); + result = sqrtf (a); + break; } if (rm == RMM) @@ -1840,6 +1865,26 @@ execute_d (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FNMSUB_D | MASK_RM: float64_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB); break; + case MATCH_FADD_D: + case MATCH_FADD_D | MASK_RM: + float64_math (cpu, rd, rs1, rs2, 0, rm, FADD); + break; + case MATCH_FSUB_D: + case MATCH_FSUB_D | MASK_RM: + float64_math (cpu, rd, rs1, rs2, 0, rm, FSUB); + break; + case MATCH_FMUL_D: + case MATCH_FMUL_D | MASK_RM: + float64_math (cpu, rd, rs1, rs2, 0, rm, FMUL); + break; + case MATCH_FDIV_D: + case MATCH_FDIV_D | MASK_RM: + float64_math (cpu, rd, rs1, rs2, 0, rm, FDIV); + break; + case MATCH_FSQRT_D: + case MATCH_FSQRT_D | MASK_RM: + float64_math (cpu, rd, rs1, rs2, 0, rm, FSQRT); + break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL); diff --git a/sim/testsuite/riscv/d-basic-arith.s b/sim/testsuite/riscv/d-basic-arith.s index 996f603e91d..2f529c68f47 100644 --- a/sim/testsuite/riscv/d-basic-arith.s +++ b/sim/testsuite/riscv/d-basic-arith.s @@ -11,9 +11,16 @@ _arg1: .double -12.5 + .double 1.5 + .double 2.2 + .double 18.5 + .double 5.0 _arg2: .double 2.5 + .double 0.5 + .double 1.1 + .double 0.1 _arg3: .double 7.45 @@ -23,6 +30,11 @@ _result: .double 38.7000008 .double -38.7000008 .double 23.7999992 + .double 2.0 + .double 1.1 + .double 1.85 + .double 185 + .double 2.2360680103302002 start .option push @@ -70,6 +82,44 @@ _result: feq.d a5,fa4,fa4 bne a5,a4,test_fail + # Test fadd instruction. + fld fa0,8(a0) + fld fa1,8(a1) + fld fa2,32(a3) + fadd.d fa4,fa0,fa1,rne + feq.d a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fsub instruction. + fld fa0,16(a0) + fld fa1,16(a1) + fld fa2,40(a3) + fsub.d fa4,fa0,fa1,rne + feq.d a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fmul instruction. + fld fa0,24(a0) + fld fa1,24(a1) + fld fa2,48(a3) + fmul.d fa4,fa0,fa1,rne + feq.d a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fdiv instruction. + fld fa0,24(a0) # Use same input values as of fmul + fld fa1,24(a1) + fld fa2,56(a3) + fdiv.d fa4,fa0,fa1,rne + feq.d a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fsqrt instruction. + fld fa0,32(a0) + fld fa2,64(a3) + fsqrt.d fa4,fa0,rne + feq.d a5,fa4,fa2 + bne a5,a4,test_fail test_pass: pass