diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 5d8ff9dc6ee..4d4ad82cce9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -97,6 +97,9 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1];
 #define FDIV	14
 #define FSQRT	15
 
+#define UNSIGNED	0
+#define SIGNED	1
+
 static INLINE void
 store_rd (SIM_CPU *cpu, int rd, unsigned_word val)
 {
@@ -1033,6 +1036,224 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2,
     }
 }
 
+/* Round and return the float value.  This function is used before we
+   perform any operation on the input float value.  */
+static float
+round_float_input (float value, int rm)
+{
+  float result = value;
+  if (rm == RNE)
+    {
+      float fractional_part = value - truncf (value);
+      /* Check if the number is halfway between two values.  */
+      if (fractional_part == 0.5 || fractional_part == -0.5)
+	{
+	  result = floorf (value);
+	  if (fmod (result, 2.0) != 0)
+	    result += (value > 0) ? 1.0 : -1.0;
+	}
+      else
+	result = roundf (value);
+    }
+  else if (rm == RTZ)
+    result = truncf (value);
+  else if (rm == RDN)
+    result = floorf (value);
+  else if (rm == RUP)
+    result = ceilf (value);
+  else
+    {
+      /* No direct match for RMM.  Simulate it.  */
+      float fracPart = value - (int) value;
+      if (fracPart > 0.5f || fracPart < -0.5f)
+	result = roundf (value);
+      else if (fracPart == 0.5f)
+	result = ceilf (value);
+      else if (fracPart == -0.5f)
+	result = floorf (value);
+      else
+	result = value;
+    }
+  return result;
+}
+
+/* Round and return the float value.  This function is used after we
+   perform the operation to get the result rounded.  */
+static float
+round_float_output (float value, int rm)
+{
+  float result;
+  if (rm == RNE)
+    result = value;
+  else if (rm == RTZ)
+    result = truncf (value);
+  else if (rm == RDN)
+    result = floorf (value);
+  else if (rm == RUP)
+    result = ceilf (value);
+  else
+    {
+      /* No direct match for RMM.  Simulate it.  */
+      float fracPart = value - (int) value;
+      if (fracPart > 0.5f || fracPart < -0.5f)
+	result = roundf (value);
+      else if (fracPart == 0.5f)
+	result = ceilf (value);
+      else if (fracPart == -0.5f)
+	result = floorf (value);
+      else
+	result = value;
+    }
+  return result;
+}
+
+static void
+convert_float_to_int (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm, int is_32bit)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  float src, rounded;
+  uint32_t rs1_bits;
+  rs1_bits = (uint32_t) riscv_cpu->fpregs[rs1];
+  memcpy (&src, &rs1_bits, sizeof (src));
+
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  /* Get the input rounded.  */
+  rounded = round_float_input (src, rm);
+
+  if (sign == SIGNED)
+    {
+      if (is_32bit)
+	store_rd (cpu, rd, (int) rounded);
+      else
+	store_rd (cpu, rd, (int64_t) rounded);
+    }
+  else
+    {
+      if (is_32bit)
+	store_rd (cpu, rd, (uint32_t) rounded);
+      else
+	store_rd (cpu, rd, (uint64_t) rounded);
+    }
+}
+
+static void
+convert_int_to_float (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  uint32_t rd_bits;
+  uint32_t usrc = (uint32_t) riscv_cpu->regs[rs1];
+  int32_t isrc = (int32_t) riscv_cpu->regs[rs1];
+  float result = .0f;
+  int old_rm;
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  if (rm == RMM)
+    {
+      if (sign == SIGNED)
+	{
+	  if (isrc >= 0)
+	    {
+	      fesetround (FE_UPWARD);
+	      result = (float) isrc;
+	      result = ceilf (result);
+	    }
+	  else
+	    {
+	      fesetround (FE_DOWNWARD);
+	      result = (float) isrc;
+	      result = floorf (result);
+	    }
+	}
+      else
+	{
+	  /* Since it's unsigned, it's always positive.  */
+	  fesetround (FE_UPWARD);
+	  result = (float) usrc;
+	  result = ceilf (result);
+	}
+    }
+  else
+    {
+      old_rm = set_riscv_rounding_mode (rm);
+
+      if (sign == SIGNED)
+	result = (float) isrc;
+      else
+	result = (float) usrc;
+
+      /* Get the result rounded.  */
+      result = round_float_output (result, rm);
+      /* Restore rounding mode.  */
+      fesetround (old_rm);
+    }
+  /* Store the result.  */
+  memcpy (&rd_bits, &result, sizeof (result));
+  store_fp (cpu, rd, rd_bits);
+}
+
+static void
+convert_long_to_float (SIM_CPU *cpu, int rd, int rs1, int sign,
+		      int rm)
+{
+  struct riscv_sim_cpu *riscv_cpu = RISCV_SIM_CPU (cpu);
+  uint32_t rd_bits;
+  uint64_t usrc = (uint64_t) riscv_cpu->regs[rs1];
+  int64_t isrc = (int64_t) riscv_cpu->regs[rs1];
+  float result = .0f;
+  int old_rm;
+
+  if (rm == DYN)
+    rm = riscv_cpu->csr.frm;
+
+  if (rm == RMM)
+    {
+      if (sign == SIGNED)
+	{
+	  if (isrc > 0)
+	    {
+	      fesetround (FE_UPWARD);
+	      result = (float) isrc;
+	      result = ceilf (result);
+	    }
+	  else
+	    {
+	      fesetround (FE_DOWNWARD);
+	      result = (float) isrc;
+	      result = floorf (result);
+	    }
+	}
+      else
+	{
+	  /* Since it's unsigned, it's always positive.  */
+	  fesetround (FE_UPWARD);
+	  result = (float) usrc;
+	  result = ceilf (result);
+	}
+    }
+  else
+    {
+      old_rm = set_riscv_rounding_mode (rm);
+
+      if (sign == SIGNED)
+	result = (float) isrc;
+      else
+	result = (float) usrc;
+
+      /* Get the result rounded.  */
+      result = round_float_output (result, rm);
+      /* Restore rounding mode.  */
+      fesetround (old_rm);
+    }
+  /* Store the result.  */
+  memcpy (&rd_bits, &result, sizeof (result));
+  store_fp (cpu, rd, rd_bits);
+}
+
 /* Simulate single precision floating point instructions.  */
 static sim_cia
 execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
@@ -1223,6 +1444,50 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     case MATCH_FSQRT_S | MASK_RM:
       float32_math (cpu, rd, rs1, rs2, rs3, rm, FSQRT);
       break;
+    case MATCH_FCVT_W_S:
+    case MATCH_FCVT_W_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.w.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_float_to_int (cpu, rd, rs1, SIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_WU_S:
+    case MATCH_FCVT_WU_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.wu.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_float_to_int (cpu, rd, rs1, UNSIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_S_W:
+    case MATCH_FCVT_S_W | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.w %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_int_to_float (cpu, rd, rs1, SIGNED, rm);
+      break;
+    case MATCH_FCVT_S_WU:
+    case MATCH_FCVT_S_WU | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.wu %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      convert_int_to_float (cpu, rd, rs1, UNSIGNED, rm);
+      break;
+    case MATCH_FCVT_L_S:
+    case MATCH_FCVT_L_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.l.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_float_to_int (cpu, rd, rs1, SIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_LU_S:
+    case MATCH_FCVT_LU_S | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.lu.s %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_float_to_int (cpu, rd, rs1, UNSIGNED, rm, is_32bit);
+      break;
+    case MATCH_FCVT_S_L:
+    case MATCH_FCVT_S_L | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.l %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_long_to_float (cpu, rd, rs1, SIGNED, rm);
+      break;
+    case MATCH_FCVT_S_LU:
+    case MATCH_FCVT_S_LU | MASK_RM:
+      TRACE_INSN (cpu, "fcvt.s.lu %s, %s, rm=%d;", rd_name, rs1_name, rm);
+      RISCV_ASSERT_RV64 (cpu, "insn: %s", op->name);
+      convert_long_to_float (cpu, rd, rs1, UNSIGNED, rm);
+      break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
       sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL);
diff --git a/sim/testsuite/riscv/s-conversion-l.s b/sim/testsuite/riscv/s-conversion-l.s
new file mode 100644
index 00000000000..a3b0f264d47
--- /dev/null
+++ b/sim/testsuite/riscv/s-conversion-l.s
@@ -0,0 +1,60 @@
+# Single precision conversion tests only for RV64.
+# mach: riscv64
+# sim(riscv64): --model RV64ID
+# ld(riscv64): -m elf64lriscv
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.rodata
+	.align 2
+
+_arg1:
+	.float -3e9
+	.float 3e9
+	.dword 16777217
+
+_result:
+	.dword -3000000000
+	.dword 3000000000
+	.float 16777216
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_result
+	li	a2,1
+	.option pop
+
+	# Test fcvt.l.s instruction.
+	flw	fa0,0(a0)
+	ld	a3,0(a1)
+	fcvt.l.s	a5,fa0,rne
+	bne	a5,a3,test_fail
+
+	# Test fcvt.lu.s instruction.
+	flw	fa0,4(a0)
+	ld	a3,8(a1)
+	fcvt.lu.s	a5,fa0,rne
+	bne	a5,a3,test_fail
+
+	# Test fcvt.s.l instruction.
+	ld	a3,8(a0)
+	flw	fa0,16(a1)
+	fcvt.s.l	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+	# Test fcvt.s.lu instruction.
+	ld	a3,8(a0)
+	flw	fa0,16(a1)
+	fcvt.s.l	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
diff --git a/sim/testsuite/riscv/s-conversion.s b/sim/testsuite/riscv/s-conversion.s
new file mode 100644
index 00000000000..e87059c1d2f
--- /dev/null
+++ b/sim/testsuite/riscv/s-conversion.s
@@ -0,0 +1,61 @@
+# Single precision conversion tests.
+# mach: riscv32 riscv64
+# sim(riscv32): --model RV32IF
+# sim(riscv64): --model RV64ID
+# ld(riscv32): -m elf32lriscv
+# ld(riscv64): -m elf64lriscv
+# as(riscv32): -march=rv32if
+# as(riscv64): -march=rv64id
+
+.include "testutils.inc"
+
+	.section	.rodata
+	.align 2
+
+_arg1:
+	.float 123.49
+	.word 123
+
+_result:
+	.word 123
+	.float 123.0
+
+	start
+	.option push
+	.option norelax
+	la	a0,_arg1
+	la	a1,_result
+	li	a2,1
+	.option pop
+
+	# Test fcvt.w.s instruction.
+	flw	fa0,0(a0)
+	lw	a3,0(a1)
+	fcvt.w.s	a5,fa0,rne
+	bne	a3,a5,test_fail
+
+	# Test fcvt.wu.s instruction.
+	flw	fa0,0(a0)
+	lw	a3,0(a1)
+	fcvt.wu.s	a5,fa0,rne
+	bne	a3,a5,test_fail
+
+	# Test fcvt.s.w instruction.
+	lw	a3,4(a0)
+	flw	fa0,4(a1)
+	fcvt.s.w	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+	# Test fcvt.s.wu instruction.
+	lw	a3,4(a0)
+	flw	fa0,4(a1)
+	fcvt.s.wu	fa1,a3,rne
+	feq.s	a4,fa0,fa1
+	bne	a4,a2,test_fail
+
+test_pass:
+	pass
+
+test_fail:
+	fail
