From patchwork Mon Feb 26 14:26:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 86386 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 709CB3858415 for ; Mon, 26 Feb 2024 14:28:07 +0000 (GMT) X-Original-To: gdb-patches@sourceware.org Delivered-To: gdb-patches@sourceware.org Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) by sourceware.org (Postfix) with ESMTPS id 7CB1B3858C54 for ; Mon, 26 Feb 2024 14:26:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7CB1B3858C54 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=imgtec.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7CB1B3858C54 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957610; cv=none; b=JDvkNwXRAG5t3Qie1vuqCi7PamvVAXaZcW94v+XPU1dTx4/QIAwUAJcFvPbwUN2kVOKRcws6dhU4+ynziubQhaZw6g7jarkUZuooK2wjFL1nBwghjjTIhYyU3Ti1Pr9TeApfmwFaK7tuRU9cy++lmRPuKEKdK6kHA8mCwGu6/vI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1708957610; c=relaxed/simple; bh=Lx7QBA5VoVRXFLPoBPnQa1qZxW+FM7SW9VE8RXctlIM=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=Jt2MBxu3Q7Iw86L3y1pdR5+k6otmDfAQOOP+RXafQNU3u4/L6xVTKl80+H9XP8lolMJrn1IqETcEEu0mlYutfYi4sFBc11hIGjCLiudLis4X3Kf4tEw2ExthM0BylcEBkSIG2v8mkvchrKYLHy+fRnb3X4v+0X74rschY7UjT/U= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41Q86eF6005999; Mon, 26 Feb 2024 14:26:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= dk201812; bh=OiI8mtrBIYmmIxfclv0nUKKfKNvhlyw/W9jRYFtOgtg=; b=kko ZKFuvkeJoF0iqgH42EDkbdKd8gHpMeFgXgquykSwR4h2PENxZsD42uGUYcKtGClI CH9V7mzqlA8Dp5IU6opAttV6Ud0zvXevzUdsTHxQHvzrMgONKu5UCJzjZUWqo5X6 TvddjsAurv/1ow2sIjOKwHSlZH4TRkPpUJJvt9irrT69eZfVM1IVlBobUs+r60/c 7DPIKNYP1JYJdCeZJufTHj6fQAKXAUyeMwieNfnPieGXnSmBkiS6UAOyCv1rTWn/ OxGWsqhLDvBx3ysLqJ6G1Ly01rq6Pw5Avmbiztvg1xVoddAVnnRatOSWHWXB1m4m wkwgJV5Lqv4gxbipXrw== Received: from hhmail05.hh.imgtec.org ([217.156.249.195]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 3wf7kssr69-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 26 Feb 2024 14:26:42 +0000 (GMT) Received: from hhbattarde.hh.imgtec.org (10.100.136.78) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 26 Feb 2024 14:26:41 +0000 From: To: CC: , , , Bhushan Attarde Subject: [PATCH 05/11] sim: riscv: Add single precision floating-point basic arithmetic instructions Date: Mon, 26 Feb 2024 14:26:22 +0000 Message-ID: <20240226142628.1629048-2-bhushan.attarde@imgtec.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240226142628.1629048-1-bhushan.attarde@imgtec.com> References: <20240226142628.1629048-1-bhushan.attarde@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.136.78] X-ClientProxiedBy: HHMAIL05.hh.imgtec.org (10.100.10.120) To HHMAIL05.hh.imgtec.org (10.100.10.120) X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-GUID: 055ZiPXJhh4jKy9DOMUtTk2qXQDuVbnj X-Proofpoint-ORIG-GUID: 055ZiPXJhh4jKy9DOMUtTk2qXQDuVbnj X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces+patchwork=sourceware.org@sourceware.org From: Bhushan Attarde Added simulation of following single precision floating-point instructions fadd.s, fsub.s, fmul.s, fdiv.s and fsqrt.s. Updated test file sim/testsuite/riscv/s-basic-arith.s to test these instructions. --- sim/riscv/sim-main.c | 50 ++++++++++++++++++++++++++++ sim/testsuite/riscv/s-basic-arith.s | 51 +++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index dd91431ad12..5d8ff9dc6ee 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -91,6 +91,11 @@ static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; #define FMSUB 8 #define FNMADD 9 #define FNMSUB 10 +#define FADD 11 +#define FSUB 12 +#define FMUL 13 +#define FDIV 14 +#define FSQRT 15 static INLINE void store_rd (SIM_CPU *cpu, int rd, unsigned_word val) @@ -942,6 +947,31 @@ float32_math (SIM_CPU *cpu, int rd, int rs1, int rs2, TRACE_INSN (cpu, "fmin.s %s, %s, %s;", frd_name, frs1_name, frs2_name); result = fminf (a, b); break; + case FADD: + TRACE_INSN (cpu, "fadd.s %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a + b; + break; + case FSUB: + TRACE_INSN (cpu, "fsub.s %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a - b; + break; + case FMUL: + TRACE_INSN (cpu, "fmul.s %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a * b; + break; + case FDIV: + TRACE_INSN (cpu, "fdiv.s %s, %s, %s, rm=%d;", + frd_name, frs1_name, frs2_name, rm); + result = a / b; + break; + case FSQRT: + TRACE_INSN (cpu, "fsqrt.s %s, %s, rm=%d;", + frd_name, frs1_name, rm); + result = sqrtf (a); + break; } if (rm == RMM) @@ -1173,6 +1203,26 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) case MATCH_FNMSUB_S | MASK_RM: float32_math (cpu, rd, rs1, rs2, rs3, rm, FNMSUB); break; + case MATCH_FADD_S: + case MATCH_FADD_S | MASK_RM: + float32_math (cpu, rd, rs1, rs2, rs3, rm, FADD); + break; + case MATCH_FSUB_S: + case MATCH_FSUB_S | MASK_RM: + float32_math (cpu, rd, rs1, rs2, rs3, rm, FSUB); + break; + case MATCH_FMUL_S: + case MATCH_FMUL_S | MASK_RM: + float32_math (cpu, rd, rs1, rs2, rs3, rm, FMUL); + break; + case MATCH_FDIV_S: + case MATCH_FDIV_S | MASK_RM: + float32_math (cpu, rd, rs1, rs2, rs3, rm, FDIV); + break; + case MATCH_FSQRT_S: + case MATCH_FSQRT_S | MASK_RM: + float32_math (cpu, rd, rs1, rs2, rs3, rm, FSQRT); + break; default: TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name); sim_engine_halt (sd, cpu, NULL, riscv_cpu->pc, sim_signalled, SIM_SIGILL); diff --git a/sim/testsuite/riscv/s-basic-arith.s b/sim/testsuite/riscv/s-basic-arith.s index a05a0d0a2c3..15d07f9e6cd 100644 --- a/sim/testsuite/riscv/s-basic-arith.s +++ b/sim/testsuite/riscv/s-basic-arith.s @@ -14,9 +14,16 @@ _arg1: .float -12.5 + .float 1.5 + .float 2.2 + .float 1.75 + .float 5.0 _arg2: .float 2.5 + .float 0.5 + .float 1.1 + .float 0.1 _arg3: .float 7.45 @@ -26,6 +33,11 @@ _result: .float 38.7000008 .float -38.7000008 .float 23.7999992 + .float 2.0 + .float 1.1 + .float 0.175 + .float 17.5 + .float 2.23606801 start .option push @@ -73,6 +85,45 @@ _result: feq.s a5,fa4,fa4 bne a5,a4,test_fail + # Test fadd instruction. + flw fa0,4(a0) + flw fa1,4(a1) + flw fa2,16(a3) + fadd.s fa4,fa0,fa1,rne + feq.s a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fsub instruction. + flw fa0,8(a0) + flw fa1,8(a1) + flw fa2,20(a3) + fsub.s fa4,fa0,fa1,rne + feq.s a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fmul instruction. + flw fa0,12(a0) + flw fa1,12(a1) + flw fa2,24(a3) + fmul.s fa4,fa0,fa1,rne + feq.s a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fdiv instruction. + flw fa0,12(a0) # Use same input values as of fmul + flw fa1,12(a1) + flw fa2,28(a3) + fdiv.s fa4,fa0,fa1,rne + feq.s a5,fa4,fa2 + bne a5,a4,test_fail + + # Test fsqrt instruction. + flw fa0,16(a0) + flw fa2,32(a3) + fsqrt.s fa4,fa0,rne + feq.s a5,fa4,fa2 + bne a5,a4,test_fail + test_pass: pass