From patchwork Thu Feb 6 22:59:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Burgess X-Patchwork-Id: 37718 Received: (qmail 105904 invoked by alias); 6 Feb 2020 22:59:07 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 105855 invoked by uid 89); 6 Feb 2020 22:59:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-22.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=H*f:sk:2054623, D*it, H*f:sk:9c6afb9, 25318 X-HELO: mail-wm1-f66.google.com Received: from mail-wm1-f66.google.com (HELO mail-wm1-f66.google.com) (209.85.128.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 06 Feb 2020 22:59:05 +0000 Received: by mail-wm1-f66.google.com with SMTP id t14so621247wmi.5 for ; Thu, 06 Feb 2020 14:59:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=Fw/ODPLfFjqGNYdpy7u7PzryZZtoDOwd7kC5q48Sgo8=; b=PAUHpXNbnLzRVXHeWnmSgIfOQpmghrHqx/uAsMH9LVh7PSnCdNWOcJuHgDfjpgCaqE d4cnR3sI4vf9x/+5fYX7x9PapKdIA42+G1phpZikgsmClOH4VAvbLLJ2zppuh8Kod0RZ ThDH92ErSt0z+DB/o7lpiINF+mtD+d1wZbzxPMVa6CQHZCV+GYmVaf7nU8+BNdFgtJUb t21CT/mj3MWjIpmbl5CvLw+H1ZYm+kHobWITLmvR8cwLRZLQTQx4p71ngmslqqYi32G4 HMES3A/xj/jkYdAqch81vwqhryHYYtTevasCiUmxZOY0PAw/KCGrpwXU33k9bRt6qldc jg+Q== Return-Path: Received: from localhost (host86-191-239-73.range86-191.btcentralplus.com. [86.191.239.73]) by smtp.gmail.com with ESMTPSA id z25sm1121371wmf.14.2020.02.06.14.59.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 06 Feb 2020 14:59:02 -0800 (PST) Date: Thu, 6 Feb 2020 22:59:01 +0000 From: Andrew Burgess To: Carlo Bramini Cc: gdb-patches@sourceware.org Subject: Re: [PATCH] Aarch64-SIM: BLR opcode does not support XLR register properly. Message-ID: <20200206225901.GH4020@embecosm.com> References: <2054623523.792939.1580901671145@mail1.libero.it> <9c6afb97-dabc-3d2f-4980-db387930a8e6@linaro.org> <1071809675.829947.1580922883716@mail1.libero.it> <1213380262.792613.1580923536993@mail1.libero.it> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1213380262.792613.1580923536993@mail1.libero.it> X-Fortune: Every absurdity has a champion who will defend it. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes * Carlo Bramini [2020-02-05 18:25:36 +0100]: > Hello, please excuse me, I just discovered that there are multiple > ChangeLog files and probably I have to provide an entry for the > right one. Sorry for my mistake in previous message. Thank you for reporting this change, and putting a patch together. I pushed this as it is such a small change, but if you wish to contribute further changes you will probably need to completing a copyright assignment[1]. A copy of what I pushed is included below. Thanks, Andrew [1] https://sourceware.org/gdb/wiki/ContributionChecklist#FSF_copyright_Assignment --- commit 69b1ffdb01106ed84a41a80f6ad2d9c26c4f45a9 Author: Carlo Bramini Date: Thu Feb 6 22:50:26 2020 +0000 sim/aarch64: Fix register ordering bug in blr (PR sim/25318) A comment in the implementation of blr says: /* The pseudo code in the spec says we update LR before fetching. the value from the rn. */ With 'rn' being the register holding the destination address. This may have been true at one point, but the ISA manual now clearly shows the destination register being read before the link register is written. This commit updates the implementation of blr to match. sim/aarch64/ChangeLog: PR sim/25318 * simulator.c (blr): Read destination register before calling aarch64_save_LR. Change-Id: Icb1c556064e3d9c807ac28440475caa205ab1064 diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 84919d6b1fc..5f16a69478c 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -13437,13 +13437,12 @@ br (sim_cpu *cpu) static void blr (sim_cpu *cpu) { - unsigned rn = INSTR (9, 5); + /* Ensure we read the destination before we write LR. */ + uint64_t target = aarch64_get_reg_u64 (cpu, INSTR (9, 5), NO_SP); TRACE_DECODE (cpu, "emulated at line %d", __LINE__); - /* The pseudo code in the spec says we update LR before fetching. - the value from the rn. */ aarch64_save_LR (cpu); - aarch64_set_next_PC (cpu, aarch64_get_reg_u64 (cpu, rn, NO_SP)); + aarch64_set_next_PC (cpu, target); if (TRACE_BRANCH_P (cpu)) {