From patchwork Wed Jun 26 13:19:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 33407 Received: (qmail 65290 invoked by alias); 26 Jun 2019 13:19:13 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 65210 invoked by uid 89); 26 Jun 2019 13:19:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 spammy=Addresses X-HELO: EUR03-AM5-obe.outbound.protection.outlook.com Received: from mail-eopbgr30082.outbound.protection.outlook.com (HELO EUR03-AM5-obe.outbound.protection.outlook.com) (40.107.3.82) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Jun 2019 13:19:09 +0000 ARC-Seal: i=1; a=rsa-sha256; s=testarcselector01; d=microsoft.com; cv=none; b=dQgXWzCXsP32fUuK7qeSE9NvwO8oH09DDpwEUAoZEQxSfwtJiXxW9EG+SobabX2wX1oQldm/CBm4vvH/fklwXOkGTA11SBJhIVoFYCgg268OuFJqJTIN1bHg+0cYe00m2Df32sUwUogm9vZ2V4sfY7IPT+nOT3PmHU+js96k3Qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=testarcselector01; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=keIhPpanWTvf2rzkx3y4Kno8A+1GFHj/OSAwwm2clno=; b=fcVmLFmCwwy5I3TlHBA7I6yR6z76rEUIgh/X/Kw9f5LA2EJvs8aVQXx8+gFOZ5luISgldrnCl8JIoqK5GX2C8ykIHwr89TR64zlFxnoMUVvvhTKhnr9XS3yIVzJ3eK7Cct+M4SCMpghTf33fILaj4PWYo9fc4YGfc6zJqxkw278= ARC-Authentication-Results: i=1; test.office365.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=keIhPpanWTvf2rzkx3y4Kno8A+1GFHj/OSAwwm2clno=; b=rxQiph6/Bz6tmdPOeC6hfKZOSbCRCvAoMEt2I7e7N91oVJdKav3zU2Y92mLhGie/xstuClhVezUbHJGNjXzlHQSnjn4HVisGOrxRjkkAQespu2tOe9KfdZv5YKP3OLMq9T+dBlI8G1rw78bzRLoG+ZVDBcVz+2rPXjVWzxPcAhQ= Received: from DB6PR0802MB2133.eurprd08.prod.outlook.com (10.172.227.22) by DB6PR0802MB2518.eurprd08.prod.outlook.com (10.172.245.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; Wed, 26 Jun 2019 13:19:05 +0000 Received: from DB6PR0802MB2133.eurprd08.prod.outlook.com ([fe80::259b:8edf:fb65:2760]) by DB6PR0802MB2133.eurprd08.prod.outlook.com ([fe80::259b:8edf:fb65:2760%8]) with mapi id 15.20.2008.017; Wed, 26 Jun 2019 13:19:05 +0000 From: Alan Hayward To: "gdb-patches@sourceware.org" CC: nd , Alan Hayward Subject: [PATCH 3/3] Arm/AArch64: Use a single set of Arm register set size defines Date: Wed, 26 Jun 2019 13:19:05 +0000 Message-ID: <20190626131821.5616-3-alan.hayward@arm.com> References: <20190626131821.5616-1-alan.hayward@arm.com> In-Reply-To: <20190626131821.5616-1-alan.hayward@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; x-ms-oob-tlc-oobclassifiers: OLM:8882; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Alan.Hayward@arm.com X-IsSubscribed: yes Both targets were using a mixture of defines and hardcoded values. Add a standard set in arch/arm.h and use throughout, ensuring that none of the existing sizes change. No functionality changes. gdb/ChangeLog: 2019-06-26 Alan Hayward * aarch32-linux-nat.h (VFP_REGS_SIZE): Remove define. * aarch64-linux-nat.c (fetch_fpregs_from_thread) (store_fpregs_to_thread) (aarch64_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE. * arch/arm.h (IWMMXT_VEC_REGISTER_SIZE, ARM_CORE_REGS_SIZE) (ARM_FP_REGS_SIZE, ARM_VFP2_REGS_SIZE, ARM_VFP3_REGS_SIZE) (IWMMXT_REGS_SIZE): Add define. * arm-linux-nat.c (IWMMXT_REGS_SIZE): Remove define. (fetch_vfp_regs, store_vfp_regs) (arm_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE. * arm-tdep.c (arm_register_g_packet_guesses): Use new defines. gdb/gdbserver/ChangeLog: 2019-06-26 Alan Hayward * linux-aarch32-low.c (arm_read_description, arm_regsets): Use new defines. * linux-arm-low.c (arm_read_description, arm_regsets): Likewise. --- gdb/aarch32-linux-nat.h | 5 ----- gdb/aarch64-linux-nat.c | 13 +++++++------ gdb/arch/arm.h | 15 +++++++++++++++ gdb/arm-linux-nat.c | 14 ++++++-------- gdb/arm-tdep.c | 15 +++------------ gdb/gdbserver/linux-aarch32-low.c | 6 +++--- gdb/gdbserver/linux-arm-low.c | 12 +++++------- 7 files changed, 39 insertions(+), 41 deletions(-) -- 2.20.1 (Apple Git-117) diff --git a/gdb/aarch32-linux-nat.h b/gdb/aarch32-linux-nat.h index 093211c812..e86593a8ad 100644 --- a/gdb/aarch32-linux-nat.h +++ b/gdb/aarch32-linux-nat.h @@ -18,11 +18,6 @@ #ifndef AARCH32_LINUX_NAT_H #define AARCH32_LINUX_NAT_H -/* Fetch and store VFP Registers. The kernel object has space for 32 - 64-bit registers, and the FPSCR. This is even when on a VFPv2 or - VFPv3D16 target. */ -#define VFP_REGS_SIZE (32 * 8 + 4) - void aarch32_gp_regcache_supply (struct regcache *regcache, uint32_t *regs, int arm_apcs_32); diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index 8ca9614301..7b60a9a0c3 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -30,6 +30,7 @@ #include "aarch64-tdep.h" #include "aarch64-linux-tdep.h" #include "aarch32-linux-nat.h" +#include "arch/arm.h" #include "nat/aarch64-linux.h" #include "nat/aarch64-linux-hw-point.h" #include "nat/aarch64-sve-linux-ptrace.h" @@ -294,7 +295,7 @@ fetch_fpregs_from_thread (struct regcache *regcache) /* Make sure REGS can hold all VFP registers contents on both aarch64 and arm. */ - gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); + gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); tid = regcache->ptid ().lwp (); @@ -302,7 +303,7 @@ fetch_fpregs_from_thread (struct regcache *regcache) if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) { - iovec.iov_len = VFP_REGS_SIZE; + iovec.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); if (ret < 0) @@ -341,14 +342,14 @@ store_fpregs_to_thread (const struct regcache *regcache) /* Make sure REGS can hold all VFP registers contents on both aarch64 and arm. */ - gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); + gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE); tid = regcache->ptid ().lwp (); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) { - iovec.iov_len = VFP_REGS_SIZE; + iovec.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); if (ret < 0) @@ -638,13 +639,13 @@ const struct target_desc * aarch64_linux_nat_target::read_description () { int ret, tid; - gdb_byte regbuf[VFP_REGS_SIZE]; + gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; struct iovec iovec; tid = inferior_ptid.lwp (); iovec.iov_base = regbuf; - iovec.iov_len = VFP_REGS_SIZE; + iovec.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); if (ret == 0) diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index 0ebbf89a9c..dfbbd56d28 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -99,6 +99,21 @@ enum arm_breakpoint_kinds /* IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ #define ARM_FP_REGISTER_SIZE 12 #define ARM_VFP_REGISTER_SIZE 8 +#define IWMMXT_VEC_REGISTER_SIZE 8 + +/* Size of register sets. */ + +/* r0-r12,sp,lr,pc,cpsr. */ +#define ARM_CORE_REGS_SIZE (17 * ARM_INT_REGISTER_SIZE) +/* f0-f8,fps. */ +#define ARM_FP_REGS_SIZE (8 * ARM_FP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) +/* d0-d15,fpscr. */ +#define ARM_VFP2_REGS_SIZE (16 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) +/* d0-d31,fpscr. */ +#define ARM_VFP3_REGS_SIZE (32 * ARM_VFP_REGISTER_SIZE + ARM_INT_REGISTER_SIZE) +/* wR0-wR15,fpscr. */ +#define IWMMXT_REGS_SIZE (16 * IWMMXT_VEC_REGISTER_SIZE \ + + 6 * ARM_INT_REGISTER_SIZE) /* Addresses for calling Thumb functions have the bit 0 set. Here are some macros to test, set, or clear bit 0 of addresses. */ diff --git a/gdb/arm-linux-nat.c b/gdb/arm-linux-nat.c index c86c97d895..a1ad6fe01e 100644 --- a/gdb/arm-linux-nat.c +++ b/gdb/arm-linux-nat.c @@ -276,8 +276,6 @@ store_regs (const struct regcache *regcache) /* Fetch all WMMX registers of the process and store into regcache. */ -#define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) - static void fetch_wmmx_regs (struct regcache *regcache) { @@ -339,7 +337,7 @@ store_wmmx_regs (const struct regcache *regcache) static void fetch_vfp_regs (struct regcache *regcache) { - gdb_byte regbuf[VFP_REGS_SIZE]; + gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; int ret, tid; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -352,7 +350,7 @@ fetch_vfp_regs (struct regcache *regcache) struct iovec iov; iov.iov_base = regbuf; - iov.iov_len = VFP_REGS_SIZE; + iov.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); } else @@ -368,7 +366,7 @@ fetch_vfp_regs (struct regcache *regcache) static void store_vfp_regs (const struct regcache *regcache) { - gdb_byte regbuf[VFP_REGS_SIZE]; + gdb_byte regbuf[ARM_VFP3_REGS_SIZE]; int ret, tid; struct gdbarch *gdbarch = regcache->arch (); struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); @@ -381,7 +379,7 @@ store_vfp_regs (const struct regcache *regcache) struct iovec iov; iov.iov_base = regbuf; - iov.iov_len = VFP_REGS_SIZE; + iov.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iov); } else @@ -398,7 +396,7 @@ store_vfp_regs (const struct regcache *regcache) struct iovec iov; iov.iov_base = regbuf; - iov.iov_len = VFP_REGS_SIZE; + iov.iov_len = ARM_VFP3_REGS_SIZE; ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iov); } else @@ -574,7 +572,7 @@ arm_linux_nat_target::read_description () registers. Support was added in 2.6.30. */ pid = inferior_ptid.lwp (); errno = 0; - buf = (char *) alloca (VFP_REGS_SIZE); + buf = (char *) alloca (ARM_VFP3_REGS_SIZE); if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) result = NULL; diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 529dd68801..fd831e4ad2 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -8794,25 +8794,16 @@ arm_register_g_packet_guesses (struct gdbarch *gdbarch) cater for remote targets whose register set layout is the same as the FPA layout. */ register_remote_g_packet_guess (gdbarch, - /* r0-r12,sp,lr,pc; f0-f7; fps,xpsr */ - (16 * ARM_INT_REGISTER_SIZE) - + (8 * ARM_FP_REGISTER_SIZE) - + (2 * ARM_INT_REGISTER_SIZE), + ARM_CORE_REGS_SIZE + ARM_FP_REGS_SIZE, tdesc_arm_with_m_fpa_layout); /* The regular M-profile layout. */ - register_remote_g_packet_guess (gdbarch, - /* r0-r12,sp,lr,pc; xpsr */ - (16 * ARM_INT_REGISTER_SIZE) - + ARM_INT_REGISTER_SIZE, + register_remote_g_packet_guess (gdbarch, ARM_CORE_REGS_SIZE, tdesc_arm_with_m); /* M-profile plus M4F VFP. */ register_remote_g_packet_guess (gdbarch, - /* r0-r12,sp,lr,pc; d0-d15; fpscr,xpsr */ - (16 * ARM_INT_REGISTER_SIZE) - + (16 * ARM_VFP_REGISTER_SIZE) - + (2 * ARM_INT_REGISTER_SIZE), + ARM_CORE_REGS_SIZE + ARM_VFP2_REGS_SIZE, tdesc_arm_with_m_vfp_d16); } diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c index 051e614c65..a932373518 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -143,10 +143,10 @@ arm_store_vfpregset (struct regcache *regcache, const void *buf) /* Register sets with using PTRACE_GETREGSET. */ static struct regset_info aarch32_regsets[] = { - { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, 18 * 4, - GENERAL_REGS, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, + ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, arm_fill_gregset, arm_store_gregset }, - { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, 32 * 8 + 4, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, arm_fill_vfpregset, arm_store_vfpregset }, NULL_REGSET diff --git a/gdb/gdbserver/linux-arm-low.c b/gdb/gdbserver/linux-arm-low.c index ff72a489cb..b323b19078 100644 --- a/gdb/gdbserver/linux-arm-low.c +++ b/gdb/gdbserver/linux-arm-low.c @@ -876,7 +876,7 @@ arm_read_description (void) /* Now make sure that the kernel supports reading these registers. Support was added in 2.6.30. */ errno = 0; - buf = (char *) xmalloc (32 * 8 + 4); + buf = (char *) xmalloc (ARM_VFP3_REGS_SIZE); if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 && errno == EIO) result = tdesc_arm; @@ -973,14 +973,12 @@ arm_get_syscall_trapinfo (struct regcache *regcache, int *sysno) /* Register sets without using PTRACE_GETREGSET. */ static struct regset_info arm_regsets[] = { - { PTRACE_GETREGS, PTRACE_SETREGS, 0, 18 * 4, - GENERAL_REGS, + { PTRACE_GETREGS, PTRACE_SETREGS, 0, + ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS, arm_fill_gregset, arm_store_gregset }, - { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, 16 * 8 + 6 * 4, - EXTENDED_REGS, + { PTRACE_GETWMMXREGS, PTRACE_SETWMMXREGS, 0, IWMMXT_REGS_SIZE, EXTENDED_REGS, arm_fill_wmmxregset, arm_store_wmmxregset }, - { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, 32 * 8 + 4, - EXTENDED_REGS, + { PTRACE_GETVFPREGS, PTRACE_SETVFPREGS, 0, ARM_VFP3_REGS_SIZE, EXTENDED_REGS, arm_fill_vfpregset, arm_store_vfpregset }, NULL_REGSET };