From patchwork Thu Dec 13 02:49:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 30658 Received: (qmail 33117 invoked by alias); 13 Dec 2018 02:49:51 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 33098 invoked by uid 89); 13 Dec 2018 02:49:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=verifying, LONGEST, HX-Received:9e19, Hx-spam-relays-external:209.85.210.194 X-HELO: mail-pf1-f194.google.com Received: from mail-pf1-f194.google.com (HELO mail-pf1-f194.google.com) (209.85.210.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Dec 2018 02:49:49 +0000 Received: by mail-pf1-f194.google.com with SMTP id b7so307228pfi.8 for ; Wed, 12 Dec 2018 18:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=XZPY9NLdxRIEBgLCnjvBAXzWhNbdSm2SRhWuYiN61z4=; b=f/05RpSPbZry007pzjV6lYfBtpmTn+k9hOAlYn/FKVSoc2x6ci+y9OYQ4a2XmztiFk y2hz9c5/Bi069mNgg0MVFj9tkq+vZPHCLLQHkjWiFX3iNgWFXu1gBc4Q7y70KlLIVqu6 RI+zC23cYUSg5/zl0p+EqaNBwCvtuFrFDoYRzeXAN2XD9lXIZ75lkycmsGGXKuEbRkNk C3gFP+O0d6jZNQgSZ+jWrCNBklSgAdrNiR9Fd9c2F+fD4q5YCPx0hMR9FxwNITs1dFUE DTTlA7axYl/yiJZf5JFsOW344kMxQLix6jvBLLdoEKypvIBZamXbdykxvBEIZ2DSbbpg 7ggw== Return-Path: Received: from rohan.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id p77sm98931pfi.85.2018.12.12.18.49.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Dec 2018 18:49:46 -0800 (PST) From: Jim Wilson To: gdb-patches@sourceware.org Cc: andrew.burgess@embecosm.com, Jim Wilson Subject: [PATCH] RISC-V: Correct printing of MSTATUS and MISA. Date: Wed, 12 Dec 2018 18:49:43 -0800 Message-Id: <20181213024943.15628-1-jimw@sifive.com> With my proposed qemu patches to make the RISC-V qemu gdbstub support work, I noticed that a 64-bit MISA was printing wrong. "info registers misa" would give me RV16ACDFIMSU. The problem here is that the MXL field is always in the upper two bits of the register, but the code assumes it is in bits 31 and 30, which is only correct for a 32-bit target. I copied code from the MSTATUS support to fix this, and also noticed a bug in it. register_size returns size in bytes, so we have to multiply by 8 to get size in bits. Tested by hand with qemu with my gdbstub patches applied, for both 32-bit and 64-bit targets, printing MISA and verifying I get the right result back. Also testing with a riscv64-linux gdb make check, with no regressions, though that only proves I didn't break anything, since a user mode gdb can't read machine registers. OK? Jim gdb/ * riscv-tdep.c (riscv_print_one_register_info): For MSTATUS, add comment for SD field, and correct xlen calculation. For MISA, add comment for MXL field, add call to register_size, and correct base calculation. --- gdb/riscv-tdep.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 5ddec70307..41b6de1c4e 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -701,8 +701,10 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, int size = register_size (gdbarch, regnum); unsigned xlen; + /* The SD field is always in the upper bit of MSTATUS, regardless + of the number of bits in MSTATUS. */ d = value_as_long (val); - xlen = size * 4; + xlen = size * 8; fprintf_filtered (file, "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X " "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X " @@ -731,9 +733,13 @@ riscv_print_one_register_info (struct gdbarch *gdbarch, int base; unsigned xlen, i; LONGEST d; + int size = register_size (gdbarch, regnum); + /* The MXL field is always in the upper two bits of MISA, + regardless of the number of bits in MISA. Mask out other + bits to ensure we have a positive value. */ d = value_as_long (val); - base = d >> 30; + base = (d >> ((size * 8) - 2)) & 0x3; xlen = 16; for (; base > 0; base--)