From patchwork Sat Nov 3 03:20:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 30014 Received: (qmail 100425 invoked by alias); 3 Nov 2018 03:20:44 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 100392 invoked by uid 89); 3 Nov 2018 03:20:39 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=sk:riscv_l, RV64GC, rv64gc, Hx-spam-relays-external:209.85.215.195 X-HELO: mail-pg1-f195.google.com Received: from mail-pg1-f195.google.com (HELO mail-pg1-f195.google.com) (209.85.215.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 03 Nov 2018 03:20:38 +0000 Received: by mail-pg1-f195.google.com with SMTP id k1-v6so1778186pgq.1 for ; Fri, 02 Nov 2018 20:20:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=H+ta4gb8h9voBPdJqYJCWxjScaxCV4wJ+54K9g+V7y8=; b=m89/Mi2bgrx3KgFFlEJENbbB/nSxIPmxM8SBd71f35C/Biw/nrwrE+BEe3XkBfBtvu JSzSHijlQYy2u7Sumzqv2i6LeoZ8TW/4ZdJM64ZaWdhnpmWGUd0QoGVlyuBbzBb0SrMB f9Bjlq30vFyARCgVx2ZokC8qYOSItLPM+zLIixpKGXs/EY0AlmstDLLRODgMRc9SgXDK 5ltAYlUQY2CBbVEFWdTgzfz/Z5LOHtIGCHh9XmRVmWmIRK45+01WUVS3mxEjJFdOfWnD ga+PzZw8RvzEqVLBgT8qtAohJ2PIVPIPSw7e0RfZSPZK7sTNg8Prn2NXJHsOhWteoUNy N+YA== Return-Path: Received: from rohan.hsd1.ca.comcast.net ([2601:646:c100:8240:ea:3ff3:d04b:a7d0]) by smtp.gmail.com with ESMTPSA id m3-v6sm14460630pgj.52.2018.11.02.20.20.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Nov 2018 20:20:36 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Fix xlen to flen typo in FP reg handling. Date: Fri, 2 Nov 2018 20:20:33 -0700 Message-Id: <20181103032033.21653-1-jimw@sifive.com> This fixes a bug in FP register handling for targets where xlen != flen. Tested against riscv-test/debug where it fixes a few failures. Also tested on RV64GC linux with the gdb testsuite where it has no effect. gdb/ * riscv-tdep.c (riscv_register_type): Use riscv_isa_flen for FP regs not riscv_isa_xlen. --- gdb/riscv-tdep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index db372e2163..b94802aa97 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -630,7 +630,7 @@ riscv_register_type (struct gdbarch *gdbarch, int regnum) } else if (regnum <= RISCV_LAST_FP_REGNUM) { - regsize = riscv_isa_xlen (gdbarch); + regsize = riscv_isa_flen (gdbarch); switch (regsize) { case 4: