From patchwork Thu Nov 1 21:41:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 29999 Received: (qmail 38811 invoked by alias); 1 Nov 2018 21:41:50 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38802 invoked by uid 89); 1 Nov 2018 21:41:49 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=simulator, 2-byte, HX-Received:sk:y10-v6m, 2byte X-HELO: mail-pg1-f195.google.com Received: from mail-pg1-f195.google.com (HELO mail-pg1-f195.google.com) (209.85.215.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 01 Nov 2018 21:41:47 +0000 Received: by mail-pg1-f195.google.com with SMTP id r9-v6so9634868pgv.6 for ; Thu, 01 Nov 2018 14:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=sUD2xZlWVGs3NoXASYqBRszwJgOAmA2cwjbPPz8AQDg=; b=ZUa9aTeYyDSm3c7+WfH7z/BWgXoyom2zGNfXbMHar+CD2150XDrroAVnpcs4jKeQtg 1L5LUY39CIZpKR1cpImXlWO4xDIYiepDwtlaVexF2+6uAC8HGVfXfDiwOPEDpjFzzqXk b7M73frqU7Q6b7bVbrawIQQo7ZlhFFKMwYiZKQgGoieKARnqBkZIDnEiPmPe9nyuW37p 8iQBzPsPaqxx32Ubg01BjzLBtzRcICiVmq54Wr6J34D8JSaa6CCwMxf7LdAVWVdTaP2/ TnCNv0xfUHCXsU3hCAO3cI8oz9dLjafOi2vDzqYbr2x7Y6zmO13IGVFrUrJuoVLtadZP IRZw== Return-Path: Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id m10-v6sm66609437pfg.180.2018.11.01.14.41.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 01 Nov 2018 14:41:45 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: Jim Wilson Subject: [PATCH] RISC-V: Don't allow unaligned breakpoints. Date: Thu, 1 Nov 2018 14:41:39 -0700 Message-Id: <20181101214139.27196-1-jimw@sifive.com> Some hardware doesn't support unaligned accesses, and a bare metal target may not have an unaligned access trap handler. So if the PC is 2-byte aligned, then use a 2-byte breakpoint to avoid unaligned accesses. Tested on native RV64GC Linux with gdb testsuite and cross on spike simulator and openocd with riscv-tests/debug. gdb/ * riscv-tdep.c (riscv_breakpoint_kind_from_pc): New local unaligned_p. Set if pcptr if unaligned. Return 2 if unaligned_p true. Update debugging messages. --- gdb/riscv-tdep.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 4b5f38a877..9c6872d021 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -415,18 +415,33 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) { if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO) { + bool unaligned_p = false; gdb_byte buf[1]; - /* Read the opcode byte to determine the instruction length. */ - read_code (*pcptr, buf, 1); + /* Some targets don't support unaligned reads. If the instruction + address is unaligned, use a compressed breakpoint. */ + if (*pcptr & 0x2) + unaligned_p = true; + else + { + /* Read the opcode byte to determine the instruction length. */ + read_code (*pcptr, buf, 1); + } if (riscv_debug_breakpoints) - fprintf_unfiltered - (gdb_stdlog, - "Using %s for breakpoint at %s (instruction length %d)\n", - riscv_insn_length (buf[0]) == 2 ? "C.EBREAK" : "EBREAK", - paddress (gdbarch, *pcptr), riscv_insn_length (buf[0])); - if (riscv_insn_length (buf[0]) == 2) + { + const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2 + ? "C.EBREAK" : "EBREAK"); + + fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ", + bp, paddress (gdbarch, *pcptr)); + if (unaligned_p) + fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n"); + else + fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n", + riscv_insn_length (buf[0])); + } + if (unaligned_p || riscv_insn_length (buf[0]) == 2) return 2; else return 4;