From patchwork Mon Oct 22 22:32:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pedro Franco de Carvalho X-Patchwork-Id: 29842 Received: (qmail 39646 invoked by alias); 22 Oct 2018 22:54:34 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 39627 invoked by uid 89); 22 Oct 2018 22:54:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KHOP_DYNAMIC, RCVD_IN_DNSWL_LOW, SPF_PASS, UNSUBSCRIBE_BODY autolearn=ham version=3.3.2 spammy=Big, opened, 1995, dat X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 22 Oct 2018 22:54:29 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w9MMTEbM120213 for ; Mon, 22 Oct 2018 18:33:43 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2n9msj63mx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 22 Oct 2018 18:33:43 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 22 Oct 2018 16:33:39 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp07028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w9MMXbRB45154538 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Oct 2018 15:33:37 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0AD31C6055; Mon, 22 Oct 2018 22:33:37 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 72812C6059; Mon, 22 Oct 2018 22:33:36 +0000 (GMT) Received: from pedro.localdomain (unknown [9.85.173.33]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 22 Oct 2018 22:33:36 +0000 (GMT) Received: by pedro.localdomain (Postfix, from userid 1000) id A9E6F3C055E; Mon, 22 Oct 2018 19:33:30 -0300 (-03) From: Pedro Franco de Carvalho To: gdb-patches@sourceware.org Cc: uweigand@de.ibm.com, edjunior@gmail.com Subject: [PATCH v5 10/12] [PowerPC] Add support for EBB and PMU registers Date: Mon, 22 Oct 2018 19:32:40 -0300 In-Reply-To: <20181022223242.7858-1-pedromfc@linux.ibm.com> References: <20181022223242.7858-1-pedromfc@linux.ibm.com> x-cbid: 18102222-0004-0000-0000-000014A2E318 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009918; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000268; SDB=6.01106526; UDB=6.00573028; IPR=6.00886611; MB=3.00023862; MTD=3.00000008; XFM=3.00000015; UTC=2018-10-22 22:33:41 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18102222-0005-0000-0000-0000893FF029 Message-Id: <20181022223242.7858-11-pedromfc@linux.ibm.com> From: Edjunior Barbosa Machado This patch adds support for registers of the Event Based Branching and Performance Monitoring Units for the powerpc linux native and core file targets, and for the powerpc linux server stub. All three EBB registers are accessible. Only a subset of the PMU registers can be accessed through ptrace. Because of this, the PMU registers are enumerated individually in gdbarch_tdep, as opposed to having a single "have_pmu" flag. This is intended to make it easier to add additional PMU registers in the future, since checking a "have_pmu" flag elsewhere in the code would no longer be correct. The tdesc feature is named org.gnu.gdb.power.linux.pmu because of this. It's unclear if it makes sense to save and restore these registers across function calls, since some of them can be modified asynchronously. They are also not tracked in record-replay mode. The kernel can return ENODATA when ptrace is used to get the EBB registers, unless a linux performance event that uses EBB is open in the inferior. For this reason, the "fill" functions in the server stub for the ebb register sets is not implemented. Since gdbserver writes all registers in one go before resuming the inferior, this error would not be detected at the time the user tries to write to one of the registers on the client side, and gdbserver would print out warnings every time it resumes the inferior when no ebb performance event is opened, so there is currently no straightforward way to handle this case. This means the ebb registers in the client-side regcache can become dirty when the user tries to write to them, until the inferior is resumed and stopped again. A related issue is that 'G' packets used to write to unrelated registers will include bad data for the EBB registers if they are unavailable, since no register status information is included in the 'G' packet. This data won't be written to the inferior by the gdbserver stub because the "fill" functions are not implemented, and currently the gdbserver stub doesn't change the status of the registers in its own regcache in response to 'G' packets. Another limitation for the ebb registers is that traceframes don't record if registers are available or not, so if these registers are collected when a tracepoint is hit and the inferior has no ebb event opened, the user will see zero values for all of them, instead of the usual . Because these registers are often unavailable, trying to store them with target_store_registers with -1 for the regno argument (all registers) would almost always fail, so they are ignored in this case. gdb/ChangeLog: YYYY-MM-DD Edjunior Barbosa Machado Pedro Franco de Carvalho * arch/ppc-linux-common.h (PPC_LINUX_SIZEOF_EBBREGSET) (PPC_LINUX_SIZEOF_PMUREGSET): Declare. * nat/ppc-linux.h (PPC_FEATURE2_EBB, NT_PPC_EBB, NT_PPC_PMU): Define if not already defined. * features/rs6000/power-ebb.xml: New file. * features/rs6000/power-linux-pmu.xml: New file. * features/rs6000/powerpc-isa207-vsx32l.xml: Include ebb and pmu features. * features/rs6000/powerpc-isa207-vsx64l.xml: Likewise. * features/rs6000/powerpc-isa207-vsx32l.c: Re-generate. * features/rs6000/powerpc-isa207-vsx64l.c: Re-generate. * regformats/rs6000/powerpc-isa207-vsx32l.dat: Re-generate. * regformats/rs6000/powerpc-isa207-vsx64l.dat: Re-generate. * ppc-linux-nat.c (fetch_register, fetch_ppc_registers): Call fetch_regset with ebb and pmu regsets. (store_register, store_ppc_registers): Call store_regset with ebb and pmu regsets. (ppc_linux_nat_target::read_description): Set isa207 field in the features struct if ebb and pmu are avaiable. * ppc-linux-tdep.c (ppc32_regmap_ebb, ppc32_regmap_pmu) (ppc32_linux_ebbregset, ppc32_linux_pmuregset): New globals. (ppc_linux_iterate_over_regset_sections): Call back with the ebb and pmu regsets. (ppc_linux_core_read_description): Check if the pmu section is present and set isa207 in the features struct. * ppc-linux-tdep.h (ppc32_linux_ebbregset) (ppc32_linux_pmuregset): Declare. * ppc-tdep.h (struct gdbarch_tdep) : New field. : New fields. : New field. (enum): : New enum values. : New enum values. : New enum values. (PPC_IS_EBB_REGNUM, PPC_IS_PMU_REGNUM): Define. * rs6000-tdep.c (rs6000_gdbarch_init): Look for and validate the ebb and pmu features. gdb/gdbserver/ChangeLog: YYYY-MM-DD Pedro Franco de Carvalho * configure.srv (powerpc*-*-linux*): Add rs6000/power-ebb.xml and rs6000/power-linux-pmu.xml to srv_xmlfiles. * linux-ppc-low.c (ppc_store_ebbregset, ppc_fill_pmuregset) (ppc_store_pmuregset): New functions. (ppc_regsets): Add entries for ebb and pmu regsets. (ppc_arch_setup): Set isa207 in features struct if the ebb and pmu regsets are available. Set sizes for these regsets. gdb/doc/ChangeLog: YYYY-MM-DD Pedro Franco de Carvalho * gdb.texinfo (PowerPC Features): Describe new features "org.gnu.gdb.power.ebb" and "org.gnu.gdb.power.linux.pmu". --- gdb/arch/ppc-linux-common.h | 2 + gdb/doc/gdb.texinfo | 9 +++ gdb/features/rs6000/power-ebb.xml | 14 +++++ gdb/features/rs6000/power-linux-pmu.xml | 17 ++++++ gdb/features/rs6000/powerpc-isa207-vsx32l.c | 12 ++++ gdb/features/rs6000/powerpc-isa207-vsx32l.xml | 2 + gdb/features/rs6000/powerpc-isa207-vsx64l.c | 12 ++++ gdb/features/rs6000/powerpc-isa207-vsx64l.xml | 2 + gdb/gdbserver/configure.srv | 2 + gdb/gdbserver/linux-ppc-low.c | 74 ++++++++++++++++++++++++- gdb/nat/ppc-linux.h | 13 +++++ gdb/ppc-linux-nat.c | 58 ++++++++++++++++++- gdb/ppc-linux-tdep.c | 62 ++++++++++++++++++++- gdb/ppc-linux-tdep.h | 2 + gdb/ppc-tdep.h | 28 ++++++++++ gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat | 8 +++ gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat | 8 +++ gdb/rs6000-tdep.c | 74 ++++++++++++++++++++++++- 18 files changed, 395 insertions(+), 4 deletions(-) create mode 100644 gdb/features/rs6000/power-ebb.xml create mode 100644 gdb/features/rs6000/power-linux-pmu.xml diff --git a/gdb/arch/ppc-linux-common.h b/gdb/arch/ppc-linux-common.h index f0e4a4221f..50e9e064d0 100644 --- a/gdb/arch/ppc-linux-common.h +++ b/gdb/arch/ppc-linux-common.h @@ -33,6 +33,8 @@ struct target_desc; #define PPC_LINUX_SIZEOF_PPRREGSET 8 #define PPC_LINUX_SIZEOF_DSCRREGSET 8 #define PPC_LINUX_SIZEOF_TARREGSET 8 +#define PPC_LINUX_SIZEOF_EBBREGSET (3*8) +#define PPC_LINUX_SIZEOF_PMUREGSET (5*8) /* Check if the hwcap auxv entry indicates that isa205 is supported. */ bool ppc_linux_has_isa205 (CORE_ADDR hwcap); diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo index e91e4b81a2..b311ac16fb 100644 --- a/gdb/doc/gdb.texinfo +++ b/gdb/doc/gdb.texinfo @@ -43135,6 +43135,15 @@ contain the 64-bit register @samp{dscr}. The @samp{org.gnu.gdb.power.tar} feature is optional. It should contain the 64-bit register @samp{tar}. +The @samp{org.gnu.gdb.power.ebb} feature is optional. It should +contain registers @samp{bescr}, @samp{ebbhr} and @samp{ebbrr}, all +64-bit wide. + +The @samp{org.gnu.gdb.power.linux.pmu} feature is optional. It should +contain registers @samp{mmcr0}, @samp{mmcr2}, @samp{siar}, @samp{sdar} +and @samp{sier}, all 64-bit wide. This is the subset of the isa 2.07 +server PMU registers provided by @sc{gnu}/Linux. + @node S/390 and System z Features @subsection S/390 and System z Features @cindex target descriptions, S/390 features diff --git a/gdb/features/rs6000/power-ebb.xml b/gdb/features/rs6000/power-ebb.xml new file mode 100644 index 0000000000..7bec21f916 --- /dev/null +++ b/gdb/features/rs6000/power-ebb.xml @@ -0,0 +1,14 @@ + + + + + + + + + + diff --git a/gdb/features/rs6000/power-linux-pmu.xml b/gdb/features/rs6000/power-linux-pmu.xml new file mode 100644 index 0000000000..c60b44462d --- /dev/null +++ b/gdb/features/rs6000/power-linux-pmu.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.c b/gdb/features/rs6000/powerpc-isa207-vsx32l.c index 73c7a01077..8fe0f5e438 100644 --- a/gdb/features/rs6000/powerpc-isa207-vsx32l.c +++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.c @@ -199,5 +199,17 @@ initialize_tdesc_powerpc_isa207_vsx32l (void) feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar"); tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64"); + feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb"); + tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux.pmu"); + tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64"); + tdesc_powerpc_isa207_vsx32l = result; } diff --git a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml index 599e6a24a2..635eef52ee 100644 --- a/gdb/features/rs6000/powerpc-isa207-vsx32l.xml +++ b/gdb/features/rs6000/powerpc-isa207-vsx32l.xml @@ -16,4 +16,6 @@ + + diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.c b/gdb/features/rs6000/powerpc-isa207-vsx64l.c index 9c735522d2..0af1879e10 100644 --- a/gdb/features/rs6000/powerpc-isa207-vsx64l.c +++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.c @@ -199,5 +199,17 @@ initialize_tdesc_powerpc_isa207_vsx64l (void) feature = tdesc_create_feature (result, "org.gnu.gdb.power.tar"); tdesc_create_reg (feature, "tar", 141, 1, NULL, 64, "uint64"); + feature = tdesc_create_feature (result, "org.gnu.gdb.power.ebb"); + tdesc_create_reg (feature, "bescr", 142, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "ebbhr", 143, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "ebbrr", 144, 0, NULL, 64, "uint64"); + + feature = tdesc_create_feature (result, "org.gnu.gdb.power.linux.pmu"); + tdesc_create_reg (feature, "mmcr0", 145, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "mmcr2", 146, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "siar", 147, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "sdar", 148, 0, NULL, 64, "uint64"); + tdesc_create_reg (feature, "sier", 149, 0, NULL, 64, "uint64"); + tdesc_powerpc_isa207_vsx64l = result; } diff --git a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml index 42a23cc001..67dff71fe2 100644 --- a/gdb/features/rs6000/powerpc-isa207-vsx64l.xml +++ b/gdb/features/rs6000/powerpc-isa207-vsx64l.xml @@ -16,4 +16,6 @@ + + diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv index 7cf7cac3f5..eb5f2085f5 100644 --- a/gdb/gdbserver/configure.srv +++ b/gdb/gdbserver/configure.srv @@ -249,6 +249,8 @@ case "${target}" in srv_xmlfiles="${srv_xmlfiles} rs6000/power-dscr.xml" srv_xmlfiles="${srv_xmlfiles} rs6000/power-ppr.xml" srv_xmlfiles="${srv_xmlfiles} rs6000/power-tar.xml" + srv_xmlfiles="${srv_xmlfiles} rs6000/power-ebb.xml" + srv_xmlfiles="${srv_xmlfiles} rs6000/power-linux-pmu.xml" srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-e500l.xml" srv_xmlfiles="${srv_xmlfiles} rs6000/power-spe.xml" srv_xmlfiles="${srv_xmlfiles} rs6000/powerpc-64l.xml" diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c index eeba724777..e32815169d 100644 --- a/gdb/gdbserver/linux-ppc-low.c +++ b/gdb/gdbserver/linux-ppc-low.c @@ -545,6 +545,61 @@ ppc_store_tarregset (struct regcache *regcache, const void *buf) supply_register_by_name (regcache, "tar", tar); } +/* Event-Based Branching regset store function. Unless the inferior + has a perf event open, ptrace can return in error when reading and + writing to the regset, with ENODATA. For reading, the registers + will correctly show as unavailable. For writing, gdbserver + currently only caches any register writes from P and G packets and + the stub always tries to write all the regsets when resuming the + inferior, which would result in frequent warnings. For this + reason, we don't define a fill function. This also means that the + client-side regcache will be dirty if the user tries to write to + the EBB registers. G packets that the client sends to write to + unrelated registers will also include data for EBB registers, even + if they are unavailable. */ + +static void +ppc_store_ebbregset (struct regcache *regcache, const void *buf) +{ + const char *regset = (const char *) buf; + + /* The order in the kernel regset is: EBBRR, EBBHR, BESCR. In the + .dat file is BESCR, EBBHR, EBBRR. */ + supply_register_by_name (regcache, "ebbrr", ®set[0]); + supply_register_by_name (regcache, "ebbhr", ®set[8]); + supply_register_by_name (regcache, "bescr", ®set[16]); +} + +/* Performance Monitoring Unit regset fill function. */ + +static void +ppc_fill_pmuregset (struct regcache *regcache, void *buf) +{ + char *regset = (char *) buf; + + /* The order in the kernel regset is SIAR, SDAR, SIER, MMCR2, MMCR0. + In the .dat file is MMCR0, MMCR2, SIAR, SDAR, SIER. */ + collect_register_by_name (regcache, "siar", ®set[0]); + collect_register_by_name (regcache, "sdar", ®set[8]); + collect_register_by_name (regcache, "sier", ®set[16]); + collect_register_by_name (regcache, "mmcr2", ®set[24]); + collect_register_by_name (regcache, "mmcr0", ®set[32]); +} + +/* Performance Monitoring Unit regset store function. */ + +static void +ppc_store_pmuregset (struct regcache *regcache, const void *buf) +{ + const char *regset = (const char *) buf; + + supply_register_by_name (regcache, "siar", ®set[0]); + supply_register_by_name (regcache, "sdar", ®set[8]); + supply_register_by_name (regcache, "sier", ®set[16]); + supply_register_by_name (regcache, "mmcr2", ®set[24]); + supply_register_by_name (regcache, "mmcr0", ®set[32]); +} + static void ppc_fill_vsxregset (struct regcache *regcache, void *buf) { @@ -654,6 +709,10 @@ static struct regset_info ppc_regsets[] = { fetch them every time, but still fall back to PTRACE_PEEKUSER for the general registers. Some kernels support these, but not the newer PPC_PTRACE_GETREGS. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_EBB, 0, EXTENDED_REGS, + NULL, ppc_store_ebbregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PMU, 0, EXTENDED_REGS, + ppc_fill_pmuregset, ppc_store_pmuregset }, { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS, ppc_fill_tarregset, ppc_store_tarregset }, { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS, @@ -734,8 +793,13 @@ ppc_arch_setup (void) features.ppr_dscr = true; if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07) && (ppc_hwcap2 & PPC_FEATURE2_TAR) + && (ppc_hwcap2 & PPC_FEATURE2_EBB) && ppc_check_regset (tid, NT_PPC_TAR, - PPC_LINUX_SIZEOF_TARREGSET)) + PPC_LINUX_SIZEOF_TARREGSET) + && ppc_check_regset (tid, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET) + && ppc_check_regset (tid, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET)) features.isa207 = true; } @@ -798,6 +862,14 @@ ppc_arch_setup (void) regset->size = (features.isa207 ? PPC_LINUX_SIZEOF_TARREGSET : 0); break; + case NT_PPC_EBB: + regset->size = (features.isa207 ? + PPC_LINUX_SIZEOF_EBBREGSET : 0); + break; + case NT_PPC_PMU: + regset->size = (features.isa207 ? + PPC_LINUX_SIZEOF_PMUREGSET : 0); + break; default: break; } diff --git a/gdb/nat/ppc-linux.h b/gdb/nat/ppc-linux.h index 913a9e0bd8..c965030d91 100644 --- a/gdb/nat/ppc-linux.h +++ b/gdb/nat/ppc-linux.h @@ -60,6 +60,9 @@ #ifndef PPC_FEATURE2_TAR #define PPC_FEATURE2_TAR 0x04000000 #endif +#ifndef PPC_FEATURE2_EBB +#define PPC_FEATURE2_EBB 0x10000000 +#endif /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a configure time check. Some older glibc's (for instance 2.2.1) @@ -106,6 +109,16 @@ #define NT_PPC_DSCR 0x105 #endif +/* Event Based Branch Registers. */ +#ifndef NT_PPC_EBB +#define NT_PPC_EBB 0x106 +#endif + +/* Performance Monitor Registers. */ +#ifndef NT_PPC_PMU +#define NT_PPC_PMU 0x107 +#endif + /* Return the wordsize of the target, either 4 or 8 bytes. */ int ppc_linux_target_wordsize (int tid); diff --git a/gdb/ppc-linux-nat.c b/gdb/ppc-linux-nat.c index 850d2292d5..0bbdcdc1ef 100644 --- a/gdb/ppc-linux-nat.c +++ b/gdb/ppc-linux-nat.c @@ -666,6 +666,24 @@ fetch_register (struct regcache *regcache, int tid, int regno) &ppc32_linux_tarregset); return; } + else if (PPC_IS_EBB_REGNUM (regno)) + { + gdb_assert (tdep->have_ebb); + + fetch_regset (regcache, tid, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + return; + } + else if (PPC_IS_PMU_REGNUM (regno)) + { + gdb_assert (tdep->ppc_mmcr0_regnum != -1); + + fetch_regset (regcache, tid, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + return; + } if (regaddr == -1) { @@ -871,6 +889,14 @@ fetch_ppc_registers (struct regcache *regcache, int tid) fetch_regset (regcache, tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET, &ppc32_linux_tarregset); + if (tdep->have_ebb) + fetch_regset (regcache, tid, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + if (tdep->ppc_mmcr0_regnum != -1) + fetch_regset (regcache, tid, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); } /* Fetch registers from the child process. Fetch all registers if @@ -1078,6 +1104,24 @@ store_register (const struct regcache *regcache, int tid, int regno) &ppc32_linux_tarregset); return; } + else if (PPC_IS_EBB_REGNUM (regno)) + { + gdb_assert (tdep->have_ebb); + + store_regset (regcache, tid, regno, NT_PPC_EBB, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset); + return; + } + else if (PPC_IS_PMU_REGNUM (regno)) + { + gdb_assert (tdep->ppc_mmcr0_regnum != -1); + + store_regset (regcache, tid, regno, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + return; + } if (regaddr == -1) return; @@ -1301,6 +1345,15 @@ store_ppc_registers (const struct regcache *regcache, int tid) store_regset (regcache, tid, -1, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET, &ppc32_linux_tarregset); + + if (tdep->ppc_mmcr0_regnum != -1) + store_regset (regcache, tid, -1, NT_PPC_PMU, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset); + + /* Because the EBB registers can be unavailable, attempts to store + them here would cause this function to fail most of the time, so + we ignore them. */ } /* Fetch the AT_HWCAP entry from the aux vector. */ @@ -2429,7 +2482,10 @@ ppc_linux_nat_target::read_description () features.ppr_dscr = true; if ((hwcap2 & PPC_FEATURE2_ARCH_2_07) && (hwcap2 & PPC_FEATURE2_TAR) - && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET)) + && (hwcap2 & PPC_FEATURE2_EBB) + && check_regset (tid, NT_PPC_TAR, PPC_LINUX_SIZEOF_TARREGSET) + && check_regset (tid, NT_PPC_EBB, PPC_LINUX_SIZEOF_EBBREGSET) + && check_regset (tid, NT_PPC_PMU, PPC_LINUX_SIZEOF_PMUREGSET)) features.isa207 = true; } diff --git a/gdb/ppc-linux-tdep.c b/gdb/ppc-linux-tdep.c index 1d070dd4a4..337ba67ed0 100644 --- a/gdb/ppc-linux-tdep.c +++ b/gdb/ppc-linux-tdep.c @@ -599,6 +599,44 @@ const struct regset ppc32_linux_tarregset = { regcache_collect_regset }; +/* Event-Based Branching regmap. */ + +static const struct regcache_map_entry ppc32_regmap_ebb[] = + { + { 1, PPC_EBBRR_REGNUM, 8 }, + { 1, PPC_EBBHR_REGNUM, 8 }, + { 1, PPC_BESCR_REGNUM, 8 }, + { 0 } + }; + +/* Event-Based Branching regset. */ + +const struct regset ppc32_linux_ebbregset = { + ppc32_regmap_ebb, + regcache_supply_regset, + regcache_collect_regset +}; + +/* Performance Monitoring Unit regmap. */ + +static const struct regcache_map_entry ppc32_regmap_pmu[] = + { + { 1, PPC_SIAR_REGNUM, 8 }, + { 1, PPC_SDAR_REGNUM, 8 }, + { 1, PPC_SIER_REGNUM, 8 }, + { 1, PPC_MMCR2_REGNUM, 8 }, + { 1, PPC_MMCR0_REGNUM, 8 }, + { 0 } + }; + +/* Performance Monitoring Unit regset. */ + +const struct regset ppc32_linux_pmuregset = { + ppc32_regmap_pmu, + regcache_supply_regset, + regcache_collect_regset +}; + const struct regset * ppc_linux_gregset (int wordsize) { @@ -674,6 +712,22 @@ ppc_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg-ppc-tar", PPC_LINUX_SIZEOF_TARREGSET, PPC_LINUX_SIZEOF_TARREGSET, &ppc32_linux_tarregset, "Target Address Register", cb_data); + + /* EBB registers are unavailable when ptrace returns ENODATA. Check + availability when generating a core file (regcache != NULL). */ + if (tdep->have_ebb) + if (regcache == NULL + || REG_VALID == regcache->get_register_status (PPC_BESCR_REGNUM)) + cb (".reg-ppc-ebb", PPC_LINUX_SIZEOF_EBBREGSET, + PPC_LINUX_SIZEOF_EBBREGSET, + &ppc32_linux_ebbregset, "Event-based Branching Registers", + cb_data); + + if (tdep->ppc_mmcr0_regnum != -1) + cb (".reg-ppc-pmu", PPC_LINUX_SIZEOF_PMUREGSET, + PPC_LINUX_SIZEOF_PMUREGSET, + &ppc32_linux_pmuregset, "Performance Monitor Registers", + cb_data); } static void @@ -1088,6 +1142,7 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch, asection *ppr = bfd_get_section_by_name (abfd, ".reg-ppc-ppr"); asection *dscr = bfd_get_section_by_name (abfd, ".reg-ppc-dscr"); asection *tar = bfd_get_section_by_name (abfd, ".reg-ppc-tar"); + asection *pmu = bfd_get_section_by_name (abfd, ".reg-ppc-pmu"); if (! section) return NULL; @@ -1123,7 +1178,12 @@ ppc_linux_core_read_description (struct gdbarch *gdbarch, if (ppr && dscr) { features.ppr_dscr = true; - if (tar) + + /* We don't require the EBB note section to be present in the + core file to select isa207 because these registers could have + been unavailable when the core file was created. They will + be in the tdep but will show as unavailable. */ + if (tar && pmu) features.isa207 = true; } diff --git a/gdb/ppc-linux-tdep.h b/gdb/ppc-linux-tdep.h index d6ddf69354..cce1ddd1ef 100644 --- a/gdb/ppc-linux-tdep.h +++ b/gdb/ppc-linux-tdep.h @@ -48,5 +48,7 @@ int ppc_linux_trap_reg_p (struct gdbarch *gdbarch); extern const struct regset ppc32_linux_pprregset; extern const struct regset ppc32_linux_dscrregset; extern const struct regset ppc32_linux_tarregset; +extern const struct regset ppc32_linux_ebbregset; +extern const struct regset ppc32_linux_pmuregset; #endif /* PPC_LINUX_TDEP_H */ diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h index e2b968177e..cfe32c9e87 100644 --- a/gdb/ppc-tdep.h +++ b/gdb/ppc-tdep.h @@ -265,6 +265,15 @@ struct gdbarch_tdep /* Decimal 128 registers. */ int ppc_dl0_regnum; /* First Decimal128 argument register pair. */ + int have_ebb; + + /* PMU registers. */ + int ppc_mmcr0_regnum; + int ppc_mmcr2_regnum; + int ppc_siar_regnum; + int ppc_sdar_regnum; + int ppc_sier_regnum; + /* Offset to ABI specific location where link register is saved. */ int lr_frame_offset; @@ -321,12 +330,31 @@ enum { PPC_PPR_REGNUM = 172, PPC_DSCR_REGNUM = 173, PPC_TAR_REGNUM = 174, + + /* EBB registers. */ + PPC_BESCR_REGNUM = 175, + PPC_EBBHR_REGNUM = 176, + PPC_EBBRR_REGNUM = 177, + + /* PMU registers. */ + PPC_MMCR0_REGNUM = 178, + PPC_MMCR2_REGNUM = 179, + PPC_SIAR_REGNUM = 180, + PPC_SDAR_REGNUM = 181, + PPC_SIER_REGNUM = 182, + PPC_NUM_REGS }; /* Big enough to hold the size of the largest register in bytes. */ #define PPC_MAX_REGISTER_SIZE 64 +#define PPC_IS_EBB_REGNUM(i) \ + ((i) >= PPC_BESCR_REGNUM && (i) <= PPC_EBBRR_REGNUM) + +#define PPC_IS_PMU_REGNUM(i) \ + ((i) >= PPC_MMCR0_REGNUM && (i) <= PPC_SIER_REGNUM) + /* An instruction to match. */ struct ppc_insn_pattern diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat index 2b6e0a9c8d..0718d72d93 100644 --- a/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat +++ b/gdb/regformats/rs6000/powerpc-isa207-vsx32l.dat @@ -145,3 +145,11 @@ expedite:r1,pc 64:ppr 64:dscr 64:tar +64:bescr +64:ebbhr +64:ebbrr +64:mmcr0 +64:mmcr2 +64:siar +64:sdar +64:sier diff --git a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat index 095bd7f2d3..510c6c87da 100644 --- a/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat +++ b/gdb/regformats/rs6000/powerpc-isa207-vsx64l.dat @@ -145,3 +145,11 @@ expedite:r1,pc 64:ppr 64:dscr 64:tar +64:bescr +64:ebbhr +64:ebbrr +64:mmcr0 +64:mmcr2 +64:siar +64:sdar +64:sier diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index 00145f2023..54591dbff6 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -5817,7 +5817,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0; int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0; - int have_tar = 0; + int have_tar = 0, have_ebb = 0, have_pmu = 0; int tdesc_wordsize = -1; const struct target_desc *tdesc = info.target_desc; struct tdesc_arch_data *tdesc_data = NULL; @@ -6157,6 +6157,64 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } else have_tar = 0; + + /* Event-based Branching Registers. */ + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.power.ebb"); + if (feature != NULL) + { + static const char *const ebb_regs[] = { + "bescr", "ebbhr", "ebbrr" + }; + + valid_p = 1; + for (i = 0; i < ARRAY_SIZE (ebb_regs); i++) + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_BESCR_REGNUM + i, + ebb_regs[i]); + if (!valid_p) + { + tdesc_data_cleanup (tdesc_data); + return NULL; + } + have_ebb = 1; + } + else + have_ebb = 0; + + /* Subset of the ISA 2.07 Performance Monitor Registers provided + by Linux. */ + feature = tdesc_find_feature (tdesc, + "org.gnu.gdb.power.linux.pmu"); + if (feature != NULL) + { + valid_p = 1; + + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_MMCR0_REGNUM, + "mmcr0"); + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_MMCR2_REGNUM, + "mmcr2"); + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_SIAR_REGNUM, + "siar"); + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_SDAR_REGNUM, + "sdar"); + valid_p &= tdesc_numbered_register (feature, tdesc_data, + PPC_SIER_REGNUM, + "sier"); + + if (!valid_p) + { + tdesc_data_cleanup (tdesc_data); + return NULL; + } + have_pmu = 1; + } + else + have_pmu = 0; } /* If we have a 64-bit binary on a 32-bit target, complain. Also @@ -6354,6 +6412,20 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1; tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1; tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1; + tdep->have_ebb = have_ebb; + + /* If additional pmu registers are added, care must be taken when + setting new fields in the tdep below, to maintain compatibility + with features that only provide some of the registers. Currently + gdb access to the pmu registers is only supported in linux, and + linux only provides a subset of the pmu registers defined in the + architecture. */ + + tdep->ppc_mmcr0_regnum = have_pmu ? PPC_MMCR0_REGNUM : -1; + tdep->ppc_mmcr2_regnum = have_pmu ? PPC_MMCR2_REGNUM : -1; + tdep->ppc_siar_regnum = have_pmu ? PPC_SIAR_REGNUM : -1; + tdep->ppc_sdar_regnum = have_pmu ? PPC_SDAR_REGNUM : -1; + tdep->ppc_sier_regnum = have_pmu ? PPC_SIER_REGNUM : -1; set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);