From patchwork Fri Oct 19 21:49:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 29813 Received: (qmail 119412 invoked by alias); 19 Oct 2018 21:50:19 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 119386 invoked by uid 89); 19 Oct 2018 21:50:18 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=argloc, HX-Received:sk:v137-v6, HX-Received:618f, H*r:sk:g12-v6s X-HELO: mail-pg1-f171.google.com Received: from mail-pg1-f171.google.com (HELO mail-pg1-f171.google.com) (209.85.215.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 19 Oct 2018 21:50:17 +0000 Received: by mail-pg1-f171.google.com with SMTP id g12-v6so16309746pgs.1 for ; Fri, 19 Oct 2018 14:50:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zNNFf27QjgPbHNQWh5PTT1J/QZLDCxViaMSRkJD0VB0=; b=URaxyMXb634R9JwMFuit9A8BjA7rjVWjb/6RXc06EwcmEYPVmL+gRJrpF5r3j2Agnu zxXevBNzciCS1iETOi8EReGx2lMZtE7WhvX/ht+Xyzx8YTkXyQ/FTm0A4su3aqo+k4YW cvmmbmZ9IyEhknmA1RtP1OpxchN9JhohedHu+l9gxm/H1EpwWLCoHFJC7/yK/jN7oktz 98hS8M6ksAgq20zSU3NKEhVU3swFd4Kw1p0HtHDaZa7NFkHnoZBTdl3W3kJ3mNdCji9s MI07ETz0zcamvvZix1vyyVAB+b3vquN33+JDob70+rnxjghPoz03JxrGLKsKiyokMVd4 4itw== Return-Path: Received: from rohan.guest.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id h6-v6sm32995514pfc.6.2018.10.19.14.50.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Oct 2018 14:50:15 -0700 (PDT) From: Jim Wilson To: gdb-patches@sourceware.org Cc: Andrew Burgess , Jim Wilson Subject: [PATCH 2/2] RISC-V: NaN-box FP values smaller than an FP register. Date: Fri, 19 Oct 2018 14:49:53 -0700 Message-Id: <20181019214953.9010-1-jimw@sifive.com> In-Reply-To: References: The hardware requires that values in FP registers be NaN-boxed, so we must extend them with 1's instead of 0's as we do for integer values. gdb/ * riscv-tdep.c (riscv_push_dummy_call) : Check for value in FP reg smaller than FP reg size, and fill with -1 instead of 0. --- gdb/riscv-tdep.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index a4d732f6f9..5be889d300 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -2408,7 +2408,12 @@ riscv_push_dummy_call (struct gdbarch *gdbarch, gdb_byte tmp [sizeof (ULONGEST)]; gdb_assert (info->argloc[0].c_length <= info->length); - memset (tmp, 0, sizeof (tmp)); + /* FP values in FP registers must be NaN-boxed. */ + if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno) + && info->argloc[0].c_length < call_info.flen) + memset (tmp, -1, sizeof (tmp)); + else + memset (tmp, 0, sizeof (tmp)); memcpy (tmp, info->contents, info->argloc[0].c_length); regcache->cooked_write (info->argloc[0].loc_data.regno, tmp); second_arg_length = @@ -2447,7 +2452,12 @@ riscv_push_dummy_call (struct gdbarch *gdbarch, gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) && second_arg_length <= call_info.flen) || second_arg_length <= call_info.xlen); - memset (tmp, 0, sizeof (tmp)); + /* FP values in FP registers must be NaN-boxed. */ + if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno) + && second_arg_length < call_info.flen) + memset (tmp, -1, sizeof (tmp)); + else + memset (tmp, 0, sizeof (tmp)); memcpy (tmp, second_arg_data, second_arg_length); regcache->cooked_write (info->argloc[1].loc_data.regno, tmp); }