From patchwork Sat Oct 6 00:15:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Marsais X-Patchwork-Id: 29662 Received: (qmail 4271 invoked by alias); 6 Oct 2018 00:16:23 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 4042 invoked by uid 89); 6 Oct 2018 00:16:03 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=throws, decoding, HContent-Transfer-Encoding:8bit X-HELO: smtp.lse.epita.fr Received: from lse.epita.fr (HELO smtp.lse.epita.fr) (163.5.55.17) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 06 Oct 2018 00:15:59 +0000 Received: from localhost.localdomain (unknown [37.228.243.108]) by smtp.lse.epita.fr (Postfix) with ESMTPSA id 063AC60F46 for ; Sat, 6 Oct 2018 02:15:39 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=lse.epita.fr; s=smtp; t=1538784940; bh=9Va8MeLGechydN5IdRpVG79rrJVYEW5lZteRrFAZ/Ro=; h=From:To:Subject:Date:In-Reply-To:References:From; b=t5shs2dR1DAoehwoLDtuQmX+XZkfk7L1P1moFopF1NkzGBcrDtWsewkfVtr2pguoO 554VqIw1bXny+YZA+PnN/PMCjSa3qnbReOsTEokm+s6MlTUvxjCKsZjmNEe2AU8DZT PbGiv0CYCSSBCbJ9e+X6KWdi3QxX5DgRKIv5AiOM= From: Pierre Marsais To: gdb-patches@sourceware.org Subject: [PATCH v4 2/3] Do not mistreat instructions as cmpxchg8b Date: Sat, 6 Oct 2018 01:15:38 +0100 Message-Id: <20181006001539.32414-2-pierre.marsais@lse.epita.fr> In-Reply-To: <20181006001539.32414-1-pierre.marsais@lse.epita.fr> References: <20180921003827.1525-1-pierre.marsais@lse.epita.fr> <20181006001539.32414-1-pierre.marsais@lse.epita.fr> MIME-Version: 1.0 All x86 instructions starting with opcode 0x0f7c where considered as cmpxchg8b if ir.mod == 3, regardless of ir.reg. However, there are some instructions (such as xsavec) sharing the same opcode, but with different ir.reg. This change throws an error when recording on unsupported instructions instead of considering them as cmpxchg8b. gdb/ChangeLog: 2018-10-05 Pierre Marsais * i386-tdep.c: (i386_process_record): Improve decoding of instructions starting with 0x0f7c. --- gdb/i386-tdep.c | 76 ++++++++++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 33 deletions(-) diff --git a/gdb/i386-tdep.c b/gdb/i386-tdep.c index a9fe290307..90c78e0bbc 100644 --- a/gdb/i386-tdep.c +++ b/gdb/i386-tdep.c @@ -5477,39 +5477,49 @@ i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ if (i386_record_modrm (&ir)) return -1; - if (ir.mod == 3) - { - /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as - an extended opcode. rdrand has bits 110 (/6) and rdseed - has bits 111 (/7). */ - if (ir.reg == 6 || ir.reg == 7) - { - /* The storage register is described by the 3 R/M bits, but the - REX.B prefix may be used to give access to registers - R8~R15. In this case ir.rex_b + R/M will give us the register - in the range R8~R15. - - REX.W may also be used to access 64-bit registers, but we - already record entire registers and not just partial bits - of them. */ - I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); - /* These instructions also set conditional bits. */ - I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); - break; - } - else - { - /* We don't handle this particular instruction yet. */ - ir.addr -= 2; - opcode = opcode << 8 | ir.modrm; - goto no_support; - } - } - I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); - I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); - if (i386_record_lea_modrm (&ir)) - return -1; - I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); + switch (ir.reg) { + case 1: /* cmpxchg8b */ + if (ir.mod == 3) + { + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); + I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); + if (i386_record_lea_modrm (&ir)) + return -1; + I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); + break; + case 6: /* rdrand */ + case 7: /* rdseed */ + if (ir.mod != 3) + { + /* We don't handle this particular instruction yet. */ + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } + /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as + an extended opcode. rdrand has bits 110 (/6) and rdseed + has bits 111 (/7). */ + /* The storage register is described by the 3 R/M bits, but the + REX.B prefix may be used to give access to registers + R8~R15. In this case ir.rex_b + R/M will give us the register + in the range R8~R15. + + REX.W may also be used to access 64-bit registers, but we + already record entire registers and not just partial bits + of them. */ + I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); + /* These instructions also set conditional bits. */ + I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); + break; + default: + ir.addr -= 2; + opcode = opcode << 8 | ir.modrm; + goto no_support; + } break; case 0x50: /* push */