From patchwork Wed Sep 19 23:19:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Baldwin X-Patchwork-Id: 29482 Received: (qmail 129440 invoked by alias); 19 Sep 2018 23:21:00 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 129332 invoked by uid 89); 19 Sep 2018 23:20:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_HELO_PASS, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=permit, differing, end_catch, sk:RETURN_ X-HELO: mail.baldwin.cx Received: from bigwig.baldwin.cx (HELO mail.baldwin.cx) (96.47.65.170) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 19 Sep 2018 23:20:58 +0000 Received: from ralph.com (ralph.baldwin.cx [66.234.199.215]) by mail.baldwin.cx (Postfix) with ESMTPSA id CE4FF10B768; Wed, 19 Sep 2018 19:20:55 -0400 (EDT) From: John Baldwin To: gdb-patches@sourceware.org Cc: andrew.burgess@embecosm.com, jimw@sifive.com, palmer@sifive.com Subject: [PATCH 2/4] Fall back to a default value of 0 for the MISA register. Date: Wed, 19 Sep 2018 16:19:48 -0700 Message-Id: <20180919231950.22634-3-jhb@FreeBSD.org> In-Reply-To: <20180919231950.22634-1-jhb@FreeBSD.org> References: <20180919231950.22634-1-jhb@FreeBSD.org> X-IsSubscribed: yes The riscv architecture supports multiple architectures with differing register sizes. If the MISA register is present, the specific architecture is chosen based on its value, otherwise properties are inferred from flags in the ELF header. However, the code to read MISA throws an exception if the register is not present. This does not trip when cross-debugging a core dump, but does trigger when attempting to debug native processes if the native target does not provide MISA. MISA is a machine-mode register in RISC-V which may or may not be available to supervisor operating systems. Rather than requiring targets to always provide a fake MISA value, fallback to 0 for now. (The Linux native target currently always provides a fake value of 0 for MISA.) Longer term, the riscv architecture should perhaps add target descriptions for the various sub-architectures and permit targets to set a description. It would then only use MISA as a fallback if an explicit description is not provided. This will permit the proper register set to be used when debugging a RV32 process (where U-XLEN in SSTATUS is set to 32 bits) on an RV64 host (where XLEN in MISA indicates 64 bits) for example by using the U-XLEN field in SSTATUS to set the target description (RV32 vs RV64) for individual processes. gdb/ChangeLog: * riscv-tdep.c (riscv_read_misa_reg): Fall back to a default value of zero. --- gdb/ChangeLog | 5 +++++ gdb/riscv-tdep.c | 13 +++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index e1892f531a..9b8a5175b0 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2018-09-19 John Baldwin + + * riscv-tdep.c (riscv_read_misa_reg): Fall back to a default value + of zero. + 2018-09-19 John Baldwin * trad-frame.c (trad_frame_set_regmap, trad_frame_set_reg_regmap): diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 254914c9c7..4b385ed5da 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -317,9 +317,18 @@ riscv_read_misa_reg (bool *read_p) } CATCH (ex, RETURN_MASK_ERROR) { - /* Old cores might have MISA located at a different offset. */ - value = get_frame_register_unsigned (frame, + TRY + { + /* Old cores might have MISA located at a different offset. */ + value + = get_frame_register_unsigned (frame, RISCV_CSR_LEGACY_MISA_REGNUM); + } + CATCH (ex, RETURN_MASK_ERROR) + { + value = 0; + } + END_CATCH } END_CATCH }