From patchwork Mon Jul 30 09:25:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 28679 Received: (qmail 59029 invoked by alias); 30 Jul 2018 09:26:03 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 58921 invoked by uid 89); 30 Jul 2018 09:26:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy=fly, Supply X-HELO: EUR02-VE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr20072.outbound.protection.outlook.com (HELO EUR02-VE1-obe.outbound.protection.outlook.com) (40.107.2.72) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 30 Jul 2018 09:26:00 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=6Ki9Orj3uYkNFC1rUo8KxS6NWCsmP3BithjlfJE36fE=; b=hb0pBKRJp6iAEhdO6miC8wXHi21ouWmDbz6XLtOscZJ2hNpi1KPIof2Mjjm/O95hr/l0UMvhhdaTdisGOqvtaDMp9mFcpY4vLaV6MbqvzfZLCMXhLVKBfHecOrp5XFk3sibolbnb6lkYRGnO4bV+0K6H+dAbNBQtu0V1FAviJro= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; Received: from C02TF0U7HF1T.manchester.arm.com (217.140.106.32) by DB6PR0802MB2133.eurprd08.prod.outlook.com (2603:10a6:4:83::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.995.21; Mon, 30 Jul 2018 09:25:46 +0000 From: Alan Hayward To: gdb-patches@sourceware.org Cc: nd@arm.com, Alan Hayward Subject: [PATCH v2 3/3] Parse SVE registers in aarch64 core file reading/writing Date: Mon, 30 Jul 2018 10:25:28 +0100 Message-Id: <20180730092528.98739-4-alan.hayward@arm.com> In-Reply-To: <20180730092528.98739-1-alan.hayward@arm.com> References: <20180730092528.98739-1-alan.hayward@arm.com> MIME-Version: 1.0 Return-Path: alan.hayward@arm.com Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-IsSubscribed: yes sve_regmap cannot be global static as the size is dependant on the current vector length. 2018-07-30 Alan Hayward * aarch64-linux-tdep.c (aarch64_linux_supply_sve_regset): New function. (aarch64_linux_collect_sve_regset): Likewise. (aarch64_linux_iterate_over_regset_sections): Check for SVE. * regcache.h (regcache_map_entry_size): New function. --- gdb/aarch64-linux-tdep.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++- gdb/regcache.h | 8 ++++ 2 files changed, 118 insertions(+), 2 deletions(-) diff --git a/gdb/aarch64-linux-tdep.c b/gdb/aarch64-linux-tdep.c index f9a95950da..bd61a2d722 100644 --- a/gdb/aarch64-linux-tdep.c +++ b/gdb/aarch64-linux-tdep.c @@ -288,6 +288,85 @@ aarch64_linux_core_read_vq (struct gdbarch *gdbarch, bfd *abfd) return vq; } +/* Supply register REGNUM from BUF to REGCACHE, using the register map + in REGSET. If REGNUM is -1, do this for all registers in REGSET. + If BUF is NULL, set the registers to "unavailable" status. */ + +static void +aarch64_linux_supply_sve_regset (const struct regset *regset, + struct regcache *regcache, + int regnum, const void *buf, size_t size) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + + if (buf == nullptr) + return regcache->supply_regset (regset, regnum, nullptr, size); + gdb_assert (size > SVE_HEADER_SIZE); + + /* BUF contains an SVE header followed by a register dump of either the + passed in SVE regset or a NEON fpregset. */ + + /* Extract required fields from the header. */ + uint64_t vg = sve_vg_from_vl (SVE_HEADER_READ (buf, 2, byte_order)); + uint16_t flags = SVE_HEADER_READ (buf, 4, byte_order); + + if (regnum == -1 || regnum == AARCH64_SVE_VG_REGNUM) + regcache->raw_supply (AARCH64_SVE_VG_REGNUM, &vg); + + if (flags & 1) + { + /* Register dump is a SVE structure. */ + regcache->supply_regset (regset, regnum, + (gdb_byte *) buf + SVE_HEADER_SIZE, + size - SVE_HEADER_SIZE); + } + else + { + /* Register dump is a fpsimd structure. First clear the SVE + registers. */ + for (int i = 0; i < AARCH64_SVE_Z_REGS_NUM; i++) + regcache->raw_supply_zeroed (AARCH64_SVE_Z0_REGNUM + i); + for (int i = 0; i < AARCH64_SVE_P_REGS_NUM; i++) + regcache->raw_supply_zeroed (AARCH64_SVE_P0_REGNUM + i); + regcache->raw_supply_zeroed (AARCH64_SVE_FFR_REGNUM); + + /* Then supply the fpsimd registers. */ + regcache->supply_regset (&aarch64_linux_fpregset, regnum, + (gdb_byte *) buf + SVE_HEADER_SIZE, + size - SVE_HEADER_SIZE); + } +} + +/* Collect register REGNUM from REGCACHE to BUF, using the register + map in REGSET. If REGNUM is -1, do this for all registers in + REGSET. */ + +static void +aarch64_linux_collect_sve_regset (const struct regset *regset, + const struct regcache *regcache, + int regnum, void *buf, size_t size) +{ + struct gdbarch *gdbarch = regcache->arch (); + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + uint64_t vq = gdbarch_tdep (gdbarch)->vq; + + gdb_assert (buf != NULL); + gdb_assert (size > SVE_HEADER_SIZE); + + /* BUF starts with a SVE header prior to the register dump. */ + SVE_HEADER_WRITE (buf, 0, byte_order, size); + SVE_HEADER_WRITE (buf, 1, byte_order, size); + SVE_HEADER_WRITE (buf, 2, byte_order, sve_vl_from_vq (vq)); + SVE_HEADER_WRITE (buf, 3, byte_order, sve_vl_from_vq (vq)); + SVE_HEADER_WRITE (buf, 4, byte_order, 1); + SVE_HEADER_WRITE (buf, 5, byte_order, 0); + + /* The SVE register dump follows. */ + regcache->collect_regset (regset, regnum, (gdb_byte *) buf + SVE_HEADER_SIZE, + size - SVE_HEADER_SIZE); +} + /* Implement the "regset_from_core_section" gdbarch method. */ static void @@ -296,10 +375,39 @@ aarch64_linux_iterate_over_regset_sections (struct gdbarch *gdbarch, void *cb_data, const struct regcache *regcache) { + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + cb (".reg", AARCH64_LINUX_SIZEOF_GREGSET, AARCH64_LINUX_SIZEOF_GREGSET, &aarch64_linux_gregset, NULL, cb_data); - cb (".reg2", AARCH64_LINUX_SIZEOF_FPREGSET, AARCH64_LINUX_SIZEOF_FPREGSET, - &aarch64_linux_fpregset, NULL, cb_data); + + if (tdep->has_sve ()) + { + /* Create this on the fly in order to handle vector register sizes. */ + const struct regcache_map_entry sve_regmap[] = + { + { 32, AARCH64_SVE_Z0_REGNUM, tdep->vq * 16 }, + { 16, AARCH64_SVE_P0_REGNUM, tdep->vq * 16 / 8 }, + { 1, AARCH64_SVE_FFR_REGNUM, 4 }, + { 1, AARCH64_FPSR_REGNUM, 4 }, + { 1, AARCH64_FPCR_REGNUM, 4 }, + { 0 } + }; + + const struct regset aarch64_linux_sve_regset = + { + sve_regmap, + aarch64_linux_supply_sve_regset, aarch64_linux_collect_sve_regset, + REGSET_VARIABLE_SIZE + }; + + cb (".reg-aarch-sve", + SVE_HEADER_SIZE + regcache_map_entry_size (aarch64_linux_fpregmap), + SVE_HEADER_SIZE + regcache_map_entry_size (sve_regmap), + &aarch64_linux_sve_regset, "SVE registers", cb_data); + } + else + cb (".reg2", AARCH64_LINUX_SIZEOF_FPREGSET, AARCH64_LINUX_SIZEOF_FPREGSET, + &aarch64_linux_fpregset, NULL, cb_data); } /* Implement the "core_read_description" gdbarch method. */ diff --git a/gdb/regcache.h b/gdb/regcache.h index ea692f38b8..ef2cc478e2 100644 --- a/gdb/regcache.h +++ b/gdb/regcache.h @@ -92,6 +92,14 @@ struct regcache_map_entry int size; }; +static inline int regcache_map_entry_size (const struct regcache_map_entry *map) +{ + int size = 0; + for (int i = 0; map[i].count != 0; i++) + size += (map[i].count * map[i].size); + return size; +} + /* Special value for the 'regno' field in the struct above. */ enum