From patchwork Fri Jul 13 13:52:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pedro Franco de Carvalho X-Patchwork-Id: 28384 Received: (qmail 120403 invoked by alias); 13 Jul 2018 15:33:48 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 120378 invoked by uid 89); 13 Jul 2018 15:33:47 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 13 Jul 2018 15:33:46 +0000 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w6DDnqM5064611 for ; Fri, 13 Jul 2018 09:53:37 -0400 Received: from e31.co.us.ibm.com (e31.co.us.ibm.com [32.97.110.149]) by mx0b-001b2d01.pphosted.com with ESMTP id 2k6ub3wf8c-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 13 Jul 2018 09:53:37 -0400 Received: from localhost by e31.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Jul 2018 07:53:33 -0600 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w6DDrVGH65339482 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 13 Jul 2018 06:53:31 -0700 Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EFBC5C6057; Fri, 13 Jul 2018 07:53:30 -0600 (MDT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8C694C605D; Fri, 13 Jul 2018 07:53:30 -0600 (MDT) Received: from pedro.localdomain (unknown [9.85.180.127]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Fri, 13 Jul 2018 07:53:30 -0600 (MDT) Received: by pedro.localdomain (Postfix, from userid 1000) id 0FBE83C04B7; Fri, 13 Jul 2018 10:53:25 -0300 (-03) From: Pedro Franco de Carvalho To: gdb-patches@sourceware.org Cc: uweigand@de.ibm.com, edjunior@gmail.com Subject: [PATCH 11/17] [PowerPC] Add gdbserver support for TAR Date: Fri, 13 Jul 2018 10:52:20 -0300 In-Reply-To: <20180713135226.2321-1-pedromfc@linux.ibm.com> References: <20180713135226.2321-1-pedromfc@linux.ibm.com> x-cbid: 18071313-8235-0000-0000-00000DD1FD07 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00009363; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000266; SDB=6.01060763; UDB=6.00544525; IPR=6.00838682; MB=3.00022128; MTD=3.00000008; XFM=3.00000015; UTC=2018-07-13 13:53:34 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18071313-8236-0000-0000-000041DE1E73 Message-Id: <20180713135226.2321-12-pedromfc@linux.ibm.com> This patch extends suport for the Target Address Register to the powerpc linux gdbserver stub. gdb/gdbserver/ChangeLog: YYYY-MM-DD Pedro Franco de Carvalho * linux-ppc-tdesc-init.h (enum ppc_linux_tdesc) : New enum value. (init_registers_powerpc_isa207_vsx32l): Declare. (init_registers_powerpc_isa207_vsx64l): Declare. * linux-ppc-low.c (ppc_fill_tarregset): New function. (ppc_store_tarregset): New function. (ppc_regsets): Add entry for the TAR regset. (ppc_arch_setup): Set isa207 in features struct when needed. Set size for the TAR regsets. (ppc_get_ipa_tdesc_idx): Return PPC_TDESC_ISA207_VSX. (initialize_low_arch): Call init_registers_powerpc_isa207_vsx32l and init_registers_powerpc_isa207_vsx64l. * linux-ppc-ipa.c (get_ipa_tdesc): Handle PPC_TDESC_ISA207_VSX. (initialize_low_tracepoint): Call init_registers_powerpc_isa207_vsx32l and init_registers_powerpc_isa207_vsx64l. --- gdb/gdbserver/linux-ppc-ipa.c | 6 ++++++ gdb/gdbserver/linux-ppc-low.c | 37 +++++++++++++++++++++++++++++++++++- gdb/gdbserver/linux-ppc-tdesc-init.h | 7 +++++++ 3 files changed, 49 insertions(+), 1 deletion(-) diff --git a/gdb/gdbserver/linux-ppc-ipa.c b/gdb/gdbserver/linux-ppc-ipa.c index c8b4c3b2da..b543dceba5 100644 --- a/gdb/gdbserver/linux-ppc-ipa.c +++ b/gdb/gdbserver/linux-ppc-ipa.c @@ -193,6 +193,8 @@ get_ipa_tdesc (int idx) return tdesc_powerpc_isa205_vsx64l; case PPC_TDESC_ISA205_PPR_DSCR_VSX: return tdesc_powerpc_isa205_ppr_dscr_vsx64l; + case PPC_TDESC_ISA207_VSX: + return tdesc_powerpc_isa207_vsx64l; #else case PPC_TDESC_BASE: return tdesc_powerpc_32l; @@ -210,6 +212,8 @@ get_ipa_tdesc (int idx) return tdesc_powerpc_isa205_vsx32l; case PPC_TDESC_ISA205_PPR_DSCR_VSX: return tdesc_powerpc_isa205_ppr_dscr_vsx32l; + case PPC_TDESC_ISA207_VSX: + return tdesc_powerpc_isa207_vsx32l; case PPC_TDESC_E500: return tdesc_powerpc_e500l; #endif @@ -239,6 +243,7 @@ initialize_low_tracepoint (void) init_registers_powerpc_isa205_altivec64l (); init_registers_powerpc_isa205_vsx64l (); init_registers_powerpc_isa205_ppr_dscr_vsx64l (); + init_registers_powerpc_isa207_vsx64l (); #else init_registers_powerpc_32l (); init_registers_powerpc_altivec32l (); @@ -248,6 +253,7 @@ initialize_low_tracepoint (void) init_registers_powerpc_isa205_altivec32l (); init_registers_powerpc_isa205_vsx32l (); init_registers_powerpc_isa205_ppr_dscr_vsx32l (); + init_registers_powerpc_isa207_vsx32l (); init_registers_powerpc_e500l (); #endif } diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c index 502ce674fc..6c27368a36 100644 --- a/gdb/gdbserver/linux-ppc-low.c +++ b/gdb/gdbserver/linux-ppc-low.c @@ -510,6 +510,22 @@ ppc_store_dscrregset (struct regcache *regcache, const void *buf) } static void +ppc_fill_tarregset (struct regcache *regcache, void *buf) +{ + char *tar = (char *) buf; + + collect_register_by_name (regcache, "tar", tar); +} + +static void +ppc_store_tarregset (struct regcache *regcache, const void *buf) +{ + const char *tar = (const char *) buf; + + supply_register_by_name (regcache, "tar", tar); +} + +static void ppc_fill_vsxregset (struct regcache *regcache, void *buf) { int i, base; @@ -622,6 +638,8 @@ static struct regset_info ppc_regsets[] = { fetch them every time, but still fall back to PTRACE_PEEKUSER for the general registers. Some kernels support these, but not the newer PPC_PTRACE_GETREGS. */ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_TAR, 0, EXTENDED_REGS, + ppc_fill_tarregset, ppc_store_tarregset }, { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_PPR, 0, EXTENDED_REGS, ppc_fill_pprregset, ppc_store_pprregset }, { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PPC_DSCR, 0, EXTENDED_REGS, @@ -696,7 +714,14 @@ ppc_arch_setup (void) if ((ppc_hwcap2 & PPC_FEATURE2_DSCR) && ppc_check_regset (tid, NT_PPC_DSCR, PPC_LINUX_SIZEOF_DSCRREGSET) && ppc_check_regset (tid, NT_PPC_PPR, PPC_LINUX_SIZEOF_PPRREGSET)) - features.ppr_dscr = true; + { + features.ppr_dscr = true; + if ((ppc_hwcap2 & PPC_FEATURE2_ARCH_2_07) + && (ppc_hwcap2 & PPC_FEATURE2_TAR) + && ppc_check_regset (tid, NT_PPC_TAR, + PPC_LINUX_SIZEOF_TARREGSET)) + features.isa207 = true; + } if (ppc_hwcap & PPC_FEATURE_CELL) features.cell = true; @@ -753,6 +778,10 @@ ppc_arch_setup (void) regset->size = (features.ppr_dscr ? PPC_LINUX_SIZEOF_DSCRREGSET : 0); break; + case NT_PPC_TAR: + regset->size = (features.isa207 ? + PPC_LINUX_SIZEOF_TARREGSET : 0); + break; default: break; } @@ -3134,6 +3163,8 @@ ppc_get_ipa_tdesc_idx (void) return PPC_TDESC_ISA205_VSX; if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx64l) return PPC_TDESC_ISA205_PPR_DSCR_VSX; + if (tdesc == tdesc_powerpc_isa207_vsx64l) + return PPC_TDESC_ISA207_VSX; #endif if (tdesc == tdesc_powerpc_32l) @@ -3152,6 +3183,8 @@ ppc_get_ipa_tdesc_idx (void) return PPC_TDESC_ISA205_VSX; if (tdesc == tdesc_powerpc_isa205_ppr_dscr_vsx32l) return PPC_TDESC_ISA205_PPR_DSCR_VSX; + if (tdesc == tdesc_powerpc_isa207_vsx32l) + return PPC_TDESC_ISA207_VSX; if (tdesc == tdesc_powerpc_e500l) return PPC_TDESC_E500; @@ -3211,6 +3244,7 @@ initialize_low_arch (void) init_registers_powerpc_isa205_altivec32l (); init_registers_powerpc_isa205_vsx32l (); init_registers_powerpc_isa205_ppr_dscr_vsx32l (); + init_registers_powerpc_isa207_vsx32l (); init_registers_powerpc_e500l (); #if __powerpc64__ init_registers_powerpc_64l (); @@ -3221,6 +3255,7 @@ initialize_low_arch (void) init_registers_powerpc_isa205_altivec64l (); init_registers_powerpc_isa205_vsx64l (); init_registers_powerpc_isa205_ppr_dscr_vsx64l (); + init_registers_powerpc_isa207_vsx64l (); #endif initialize_regsets_info (&ppc_regsets_info); diff --git a/gdb/gdbserver/linux-ppc-tdesc-init.h b/gdb/gdbserver/linux-ppc-tdesc-init.h index c5c10c0670..29b8122886 100644 --- a/gdb/gdbserver/linux-ppc-tdesc-init.h +++ b/gdb/gdbserver/linux-ppc-tdesc-init.h @@ -30,6 +30,7 @@ enum ppc_linux_tdesc { PPC_TDESC_ISA205_ALTIVEC, PPC_TDESC_ISA205_VSX, PPC_TDESC_ISA205_PPR_DSCR_VSX, + PPC_TDESC_ISA207_VSX, PPC_TDESC_E500, }; @@ -59,6 +60,9 @@ void init_registers_powerpc_isa205_vsx32l (void); /* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx32l.c. */ void init_registers_powerpc_isa205_ppr_dscr_vsx32l (void); +/* Defined in auto-generated file powerpc-isa207-vsx32l.c. */ +void init_registers_powerpc_isa207_vsx32l (void); + /* Defined in auto-generated file powerpc-e500l.c. */ void init_registers_powerpc_e500l (void); @@ -90,4 +94,7 @@ void init_registers_powerpc_isa205_vsx64l (void); /* Defined in auto-generated file powerpc-isa205-ppr-dscr-vsx64l.c. */ void init_registers_powerpc_isa205_ppr_dscr_vsx64l (void); +/* Defined in auto-generated file powerpc-isa207-vsx64l.c. */ +void init_registers_powerpc_isa207_vsx64l (void); + #endif