From patchwork Wed Jun 6 15:16:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 27667 Received: (qmail 104426 invoked by alias); 6 Jun 2018 15:17:29 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 104303 invoked by uid 89); 6 Jun 2018 15:17:28 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: EUR02-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr10087.outbound.protection.outlook.com (HELO EUR02-HE1-obe.outbound.protection.outlook.com) (40.107.1.87) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 06 Jun 2018 15:17:26 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; Received: from C02TF0U7HF1T.arm.com (217.140.96.140) by AM4PR0802MB2132.eurprd08.prod.outlook.com (2603:10a6:200:5c::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.841.14; Wed, 6 Jun 2018 15:16:55 +0000 From: Alan Hayward To: gdb-patches@sourceware.org Cc: nd@arm.com, Alan Hayward Subject: [PATCH v2 09/10] Ptrace support for AArch64 SVE gdbsever Date: Wed, 6 Jun 2018 16:16:28 +0100 Message-Id: <20180606151629.36602-10-alan.hayward@arm.com> In-Reply-To: <20180606151629.36602-1-alan.hayward@arm.com> References: <20180606151629.36602-1-alan.hayward@arm.com> MIME-Version: 1.0 X-ClientProxiedBy: CWLP265CA0083.GBRP265.PROD.OUTLOOK.COM (2603:10a6:401:50::23) To AM4PR0802MB2132.eurprd08.prod.outlook.com (2603:10a6:200:5c::23) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-TrafficTypeDiagnostic: AM4PR0802MB2132: NoDisclaimer: True X-Exchange-Antispam-Report-Test: UriScan:(180628864354917); X-MS-Exchange-SenderADCheck: 1 X-Forefront-PRVS: 06952FC175 Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Office365-Filtering-Correlation-Id: 7a18bcac-92e4-41c4-afb3-08d5cbc08a79 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2018 15:16:55.7526 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a18bcac-92e4-41c4-afb3-08d5cbc08a79 X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM4PR0802MB2132 X-IsSubscribed: yes Add checks to detect SVE tdesc. Easiest way to do this is by checking the size of the vector registers. Use the common aarch64 ptrace copy functions for reading/writing registers. A wrapper is required due to the common functions using reg_buffer_common. 2018-06-06 Alan Hayward gdbserver/ * linux-aarch64-low.c (is_sve_tdesc): New function. (aarch64_sve_regs_copy_to_regcache): Likewise. (aarch64_sve_regs_copy_from_regcache): Likewise. (aarch64_regs_info): Add SVE checks. (initialize_low_arch): Initialize SVE. --- gdb/gdbserver/linux-aarch64-low.c | 62 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 59 insertions(+), 3 deletions(-) diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c index 9db9a7c1c3..e7fec25a64 100644 --- a/gdb/gdbserver/linux-aarch64-low.c +++ b/gdb/gdbserver/linux-aarch64-low.c @@ -73,6 +73,16 @@ is_64bit_tdesc (void) return register_size (regcache->tdesc, 0) == 8; } +static bool +is_sve_tdesc (void) +{ + struct regcache *regcache = get_thread_regcache (current_thread, 0); + + /* Mimimum size of Z0 on SVE is 256bit. If not SVE, then Z0 will be the + 128bit V0 register. */ + return register_size (regcache->tdesc, AARCH64_SVE_Z0_REGNUM) >= 32; +} + /* Implementation of linux_target_ops method "cannot_store_register". */ static int @@ -514,6 +524,22 @@ aarch64_arch_setup (void) aarch64_linux_get_debug_reg_capacity (lwpid_of (current_thread)); } +/* Wrapper for aarch64_sve_regs_copy_to_reg_buf. */ + +static void +aarch64_sve_regs_copy_to_regcache (struct regcache *regcache, const void *buf) +{ + return aarch64_sve_regs_copy_to_reg_buf (regcache, buf); +} + +/* Wrapper for aarch64_sve_regs_copy_from_reg_buf. */ + +static void +aarch64_sve_regs_copy_from_regcache (struct regcache *regcache, void *buf) +{ + return aarch64_sve_regs_copy_from_reg_buf (regcache, buf); +} + static struct regset_info aarch64_regsets[] = { { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, @@ -540,15 +566,44 @@ static struct regs_info regs_info_aarch64 = &aarch64_regsets_info, }; +static struct regset_info aarch64_sve_regsets[] = +{ + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS, + sizeof (struct user_pt_regs), GENERAL_REGS, + aarch64_fill_gregset, aarch64_store_gregset }, + { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_SVE, + SVE_PT_SIZE (AARCH64_MAX_SVE_VQ, SVE_PT_REGS_SVE), EXTENDED_REGS, + aarch64_sve_regs_copy_from_regcache, aarch64_sve_regs_copy_to_regcache + }, + NULL_REGSET +}; + +static struct regsets_info aarch64_sve_regsets_info = + { + aarch64_sve_regsets, /* regsets. */ + 0, /* num_regsets. */ + NULL, /* disabled_regsets. */ + }; + +static struct regs_info regs_info_aarch64_sve = + { + NULL, /* regset_bitmap. */ + NULL, /* usrregs. */ + &aarch64_sve_regsets_info, + }; + /* Implementation of linux_target_ops method "regs_info". */ static const struct regs_info * aarch64_regs_info (void) { - if (is_64bit_tdesc ()) - return ®s_info_aarch64; - else + if (!is_64bit_tdesc ()) return ®s_info_aarch32; + + if (is_sve_tdesc ()) + return ®s_info_aarch64_sve; + + return ®s_info_aarch64; } /* Implementation of linux_target_ops method "supports_tracepoints". */ @@ -3027,6 +3082,7 @@ initialize_low_arch (void) initialize_low_arch_aarch32 (); initialize_regsets_info (&aarch64_regsets_info); + initialize_regsets_info (&aarch64_sve_regsets_info); #if GDB_SELF_TEST initialize_low_tdesc ();