From patchwork Sun Apr 16 14:14:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 20053 Received: (qmail 91911 invoked by alias); 16 Apr 2017 14:15:09 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 91188 invoked by uid 89); 16 Apr 2017 14:15:00 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=Exclusive, 92122, Say, Advance X-HELO: barracuda.ebox.ca Received: from barracuda.ebox.ca (HELO barracuda.ebox.ca) (96.127.255.19) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 16 Apr 2017 14:14:39 +0000 X-ASG-Debug-ID: 1492352077-0c856e65d51ccda70001-fS2M51 Received: from smtp.electronicbox.net (smtp.electronicbox.net [96.127.255.82]) by barracuda.ebox.ca with ESMTP id 7Z1JhQMAU8NwDfBa (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 16 Apr 2017 10:14:37 -0400 (EDT) X-Barracuda-Envelope-From: simon.marchi@polymtl.ca X-Barracuda-RBL-Trusted-Forwarder: 96.127.255.82 Received: from simark.lan (173-246-11-162.qc.cable.ebox.net [173.246.11.162]) by smtp.electronicbox.net (Postfix) with ESMTP id 5F94C440E7C; Sun, 16 Apr 2017 10:14:37 -0400 (EDT) From: Simon Marchi X-Barracuda-Effective-Source-IP: 173-246-11-162.qc.cable.ebox.net[173.246.11.162] X-Barracuda-Apparent-Source-IP: 173.246.11.162 X-Barracuda-RBL-IP: 173.246.11.162 To: gdb-patches@sourceware.org Cc: Simon Marchi Subject: [PATCH 2/4] Change return type of gdbarch_software_single_step to vector Date: Sun, 16 Apr 2017 10:14:28 -0400 X-ASG-Orig-Subj: [PATCH 2/4] Change return type of gdbarch_software_single_step to vector Message-Id: <20170416141430.2585-3-simon.marchi@polymtl.ca> In-Reply-To: <20170416141430.2585-1-simon.marchi@polymtl.ca> References: <20170416141430.2585-1-simon.marchi@polymtl.ca> X-Barracuda-Connect: smtp.electronicbox.net[96.127.255.82] X-Barracuda-Start-Time: 1492352077 X-Barracuda-Encrypted: DHE-RSA-AES256-SHA X-Barracuda-URL: https://96.127.255.19:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 55169 X-Barracuda-BRTS-Status: 1 X-Barracuda-Spam-Score: 0.50 X-Barracuda-Spam-Status: No, SCORE=0.50 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=8.0 tests=BSF_RULE7568M X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.38127 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- 0.50 BSF_RULE7568M Custom Rule 7568M X-IsSubscribed: yes This is a relatively straightforward patch that changes gdbarch_software_single_step so it returns an std::vector instead of a VEC (CORE_ADDR). gdb/ChangeLog: * gdbarch.sh (software_single_step): Change return type to std::vector. * gdbarch.c, gdbarch.h: Re-generate. * arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw): Adjust. (arm_deal_with_atomic_sequence_raw): Adjust. (thumb_get_next_pcs_raw): Adjust. (arm_get_next_pcs_raw): Adjust. (arm_get_next_pcs): Adjust. * arch/arm-get-next-pcs.h (arm_get_next_pcs): Adjust. * aarch64-tdep.c (aarch64_software_single_step): Adjust. * alpha-tdep.c (alpha_deal_with_atomic_sequence): Adjust. (alpha_software_single_step): Adjust. * alpha-tdep.h (alpha_software_single_step): Adjust. * arm-linux-tdep.c (arm_linux_software_single_step): Adjust. * arm-tdep.c (arm_software_single_step): Adjust. (arm_breakpoint_kind_from_current_state): Adjust. * arm-tdep.h (arm_software_single_step): Adjust. * breakpoint.c (insert_single_step_breakpoint): Adjust. * cris-tdep.c (cris_software_single_step): Adjust. * mips-tdep.c (mips_deal_with_atomic_sequence): Adjust. (micromips_deal_with_atomic_sequence): Adjust. (deal_with_atomic_sequence): Adjust. (mips_software_single_step): Adjust. * mips-tdep.h (mips_software_single_step): Adjust. * moxie-tdep.c (moxie_software_single_step): Adjust. * nios2-tdep.c (nios2_software_single_step): Adjust. * ppc-tdep.h (ppc_deal_with_atomic_sequence): Adjust. * rs6000-aix-tdep.c (rs6000_software_single_step): Adjust. * rs6000-tdep.c (ppc_deal_with_atomic_sequence): Adjust. * s390-linux-tdep.c (s390_software_single_step): Adjust. * sparc-tdep.c (sparc_software_single_step): Adjust. * spu-tdep.c (spu_software_single_step): Adjust. * tic6x-tdep.c (tic6x_software_single_step): Adjust. gdb/gdbserver/ChangeLog: * linux-arm-low.c (arm_gdbserver_get_next_pcs): Adjust to software_single_step change of return type to std::vector. * linux-low.c (install_software_single_step_breakpoints): Likewise. * linux-low.h (install_software_single_step_breakpoints): Likewise. --- gdb/aarch64-tdep.c | 17 +++++---- gdb/alpha-tdep.c | 23 ++++++----- gdb/alpha-tdep.h | 3 +- gdb/arch/arm-get-next-pcs.c | 89 +++++++++++++++++++++---------------------- gdb/arch/arm-get-next-pcs.h | 5 ++- gdb/arm-linux-tdep.c | 21 +++------- gdb/arm-tdep.c | 30 +++------------ gdb/arm-tdep.h | 4 +- gdb/breakpoint.c | 10 ++--- gdb/cris-tdep.c | 8 ++-- gdb/gdbarch.c | 2 +- gdb/gdbarch.h | 5 ++- gdb/gdbarch.sh | 3 +- gdb/gdbserver/linux-arm-low.c | 7 +--- gdb/gdbserver/linux-low.c | 9 +---- gdb/gdbserver/linux-low.h | 2 +- gdb/mips-tdep.c | 57 +++++++++++++-------------- gdb/mips-tdep.h | 3 +- gdb/moxie-tdep.c | 26 ++++++------- gdb/nios2-tdep.c | 7 +--- gdb/ppc-tdep.h | 3 +- gdb/rs6000-aix-tdep.c | 10 ++--- gdb/rs6000-tdep.c | 15 ++++---- gdb/s390-linux-tdep.c | 15 +++----- gdb/sparc-tdep.c | 8 ++-- gdb/spu-tdep.c | 9 ++--- gdb/tic6x-tdep.c | 7 +--- 27 files changed, 176 insertions(+), 222 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 28c2573d18..ff5bc04ea2 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -2417,7 +2417,7 @@ value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) /* Implement the "software_single_step" gdbarch method, needed to single step through atomic sequences on AArch64. */ -static VEC (CORE_ADDR) * +static std::vector aarch64_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -2435,14 +2435,13 @@ aarch64_software_single_step (struct regcache *regcache) int bc_insn_count = 0; /* Conditional branch instruction count. */ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ aarch64_inst inst; - VEC (CORE_ADDR) *next_pcs = NULL; if (aarch64_decode_insn (insn, &inst, 1) != 0) - return NULL; + return {}; /* Look for a Load Exclusive instruction which begins the sequence. */ if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) - return NULL; + return {}; for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) { @@ -2451,14 +2450,14 @@ aarch64_software_single_step (struct regcache *regcache) byte_order_for_code); if (aarch64_decode_insn (insn, &inst, 1) != 0) - return NULL; + return {}; /* Check if the instruction is a conditional branch. */ if (inst.opcode->iclass == condbranch) { gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); if (bc_insn_count >= 1) - return NULL; + return {}; /* It is, so we'll try to set a breakpoint at the destination. */ breaks[1] = loc + inst.operands[0].imm.value; @@ -2477,7 +2476,7 @@ aarch64_software_single_step (struct regcache *regcache) /* We didn't find a closing Store Exclusive instruction, fall back. */ if (!closing_insn) - return NULL; + return {}; /* Insert breakpoint after the end of the atomic sequence. */ breaks[0] = loc + insn_size; @@ -2489,10 +2488,12 @@ aarch64_software_single_step (struct regcache *regcache) || (breaks[1] >= pc && breaks[1] <= closing_insn))) last_breakpoint = 0; + std::vector next_pcs; + /* Insert the breakpoint at the end of the sequence, and one at the destination of the conditional branch, if it exists. */ for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c index 7c521db24c..d62566c4b0 100644 --- a/gdb/alpha-tdep.c +++ b/gdb/alpha-tdep.c @@ -765,7 +765,7 @@ static const int stq_c_opcode = 0x2f; is found, attempt to step through it. A breakpoint is placed at the end of the sequence. */ -static VEC (CORE_ADDR) * +static std::vector alpha_deal_with_atomic_sequence (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -779,12 +779,11 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache) int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ int bc_insn_count = 0; /* Conditional branch instruction count. */ - VEC (CORE_ADDR) *next_pcs = NULL; /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ if (INSN_OPCODE (insn) != ldl_l_opcode && INSN_OPCODE (insn) != ldq_l_opcode) - return NULL; + return {}; /* Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ @@ -803,8 +802,8 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache) immediate = (immediate ^ 0x400000) - 0x400000; if (bc_insn_count >= 1) - return NULL; /* More than one branch found, fallback - to the standard single-step code. */ + return {}; /* More than one branch found, fallback + to the standard single-step code. */ breaks[1] = loc + ALPHA_INSN_SIZE + immediate; @@ -820,7 +819,7 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache) /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ if (INSN_OPCODE (insn) != stl_c_opcode && INSN_OPCODE (insn) != stq_c_opcode) - return NULL; + return {}; closing_insn = loc; loc += ALPHA_INSN_SIZE; @@ -835,8 +834,10 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache) || (breaks[1] >= pc && breaks[1] <= closing_insn))) last_breakpoint = 0; + std::vector next_pcs; + for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } @@ -1717,17 +1718,15 @@ alpha_next_pc (struct regcache *regcache, CORE_ADDR pc) return (pc + ALPHA_INSN_SIZE); } -VEC (CORE_ADDR) * +std::vector alpha_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); CORE_ADDR pc; - VEC (CORE_ADDR) *next_pcs = NULL; - pc = regcache_read_pc (regcache); + pc = alpha_next_pc (regcache, regcache_read_pc (regcache)); - VEC_safe_push (CORE_ADDR, next_pcs, alpha_next_pc (regcache, pc)); - return next_pcs; + return {pc}; } diff --git a/gdb/alpha-tdep.h b/gdb/alpha-tdep.h index ab46ba56be..5f1d103273 100644 --- a/gdb/alpha-tdep.h +++ b/gdb/alpha-tdep.h @@ -103,7 +103,8 @@ struct gdbarch_tdep }; extern unsigned int alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc); -extern VEC (CORE_ADDR) *alpha_software_single_step (struct regcache *regcache); +extern std::vector alpha_software_single_step + (struct regcache *regcache); extern CORE_ADDR alpha_after_prologue (CORE_ADDR pc); extern void alpha_mdebug_init_abi (struct gdbarch_info, struct gdbarch *); diff --git a/gdb/arch/arm-get-next-pcs.c b/gdb/arch/arm-get-next-pcs.c index 398dd59ac7..4e5234cb77 100644 --- a/gdb/arch/arm-get-next-pcs.c +++ b/gdb/arch/arm-get-next-pcs.c @@ -45,7 +45,7 @@ arm_get_next_pcs_ctor (struct arm_get_next_pcs *self, is found, attempt to step through it. The end of the sequence address is added to the next_pcs list. */ -static VEC (CORE_ADDR) * +static std::vector thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) { int byte_order_for_code = self->byte_order_for_code; @@ -58,27 +58,26 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ ULONGEST status, itstate; - VEC (CORE_ADDR) *next_pcs = NULL; /* We currently do not support atomic sequences within an IT block. */ status = regcache_raw_get_unsigned (self->regcache, ARM_PS_REGNUM); itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3); if (itstate & 0x0f) - return NULL; + return {}; /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */ insn1 = self->ops->read_mem_uint (loc, 2, byte_order_for_code); loc += 2; if (thumb_insn_size (insn1) != 4) - return NULL; + return {}; insn2 = self->ops->read_mem_uint (loc, 2, byte_order_for_code); loc += 2; if (!((insn1 & 0xfff0) == 0xe850 || ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040))) - return NULL; + return {}; /* Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ @@ -95,8 +94,8 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f) { if (last_breakpoint > 0) - return NULL; /* More than one conditional branch found, - fallback to the standard code. */ + return {}; /* More than one conditional branch found, + fallback to the standard code. */ breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1); last_breakpoint++; @@ -107,7 +106,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) Fall back to standard code to avoid losing control of execution. */ else if (thumb_instruction_changes_pc (insn1)) - return NULL; + return {}; } else { @@ -135,8 +134,8 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) offset += (imm1 << 12) + (imm2 << 1); if (last_breakpoint > 0) - return 0; /* More than one conditional branch found, - fallback to the standard code. */ + return {}; /* More than one conditional branch found, + fallback to the standard code. */ breaks[1] = loc + offset; last_breakpoint++; @@ -147,7 +146,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) Fall back to standard code to avoid losing control of execution. */ else if (thumb2_instruction_changes_pc (insn1, insn2)) - return NULL; + return {}; /* If we find a strex{,b,h,d}, we're done. */ if ((insn1 & 0xfff0) == 0xe840 @@ -158,7 +157,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ if (insn_count == atomic_sequence_length) - return NULL; + return {}; /* Insert a breakpoint right after the end of the atomic sequence. */ breaks[0] = loc; @@ -170,9 +169,11 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) || (breaks[1] >= pc && breaks[1] < loc))) last_breakpoint = 0; + std::vector next_pcs; + /* Adds the breakpoints to the list to be inserted. */ for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (breaks[index])); + next_pcs.push_back (MAKE_THUMB_ADDR (breaks[index])); return next_pcs; } @@ -182,7 +183,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) is found, attempt to step through it. The end of the sequence address is added to the next_pcs list. */ -static VEC (CORE_ADDR) * +static std::vector arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) { int byte_order_for_code = self->byte_order_for_code; @@ -194,7 +195,6 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) int index; int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ - VEC (CORE_ADDR) *next_pcs = NULL; /* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. Note that we do not currently support conditionally executed atomic @@ -203,7 +203,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) loc += 4; if ((insn & 0xff9000f0) != 0xe1900090) - return NULL; + return {}; /* Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ @@ -219,8 +219,8 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) if (bits (insn, 24, 27) == 0xa) { if (last_breakpoint > 0) - return NULL; /* More than one conditional branch found, fallback - to the standard single-step code. */ + return {}; /* More than one conditional branch found, fallback + to the standard single-step code. */ breaks[1] = BranchDest (loc - 4, insn); last_breakpoint++; @@ -230,7 +230,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) but conditional branches to change the PC. Fall back to standard code to avoid losing control of execution. */ else if (arm_instruction_changes_pc (insn)) - return NULL; + return {}; /* If we find a strex{,b,h,d}, we're done. */ if ((insn & 0xff9000f0) == 0xe1800090) @@ -239,7 +239,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) /* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */ if (insn_count == atomic_sequence_length) - return NULL; + return {}; /* Insert a breakpoint right after the end of the atomic sequence. */ breaks[0] = loc; @@ -251,16 +251,18 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self) || (breaks[1] >= pc && breaks[1] < loc))) last_breakpoint = 0; + std::vector next_pcs; + /* Adds the breakpoints to the list to be inserted. */ for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } /* Find the next possible PCs for thumb mode. */ -static VEC (CORE_ADDR) * +static std::vector thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) { int byte_order = self->byte_order; @@ -272,7 +274,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) unsigned long offset; ULONGEST status, itstate; struct regcache *regcache = self->regcache; - VEC (CORE_ADDR) * next_pcs = NULL; + std::vector next_pcs; nextpc = MAKE_THUMB_ADDR (nextpc); pc_val = MAKE_THUMB_ADDR (pc_val); @@ -315,7 +317,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) itstate = thumb_advance_itstate (itstate); } - VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc)); + next_pcs.push_back (MAKE_THUMB_ADDR (pc)); return next_pcs; } else if (itstate != 0) @@ -335,7 +337,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) itstate = thumb_advance_itstate (itstate); } - VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc)); + next_pcs.push_back (MAKE_THUMB_ADDR (pc)); return next_pcs; } else if ((itstate & 0x0f) == 0x08) @@ -361,7 +363,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) /* Set a breakpoint on the following instruction. */ gdb_assert ((itstate & 0x0f) != 0); - VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc)); + next_pcs.push_back (MAKE_THUMB_ADDR (pc)); cond_negated = (itstate >> 4) & 1; @@ -378,7 +380,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) } while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated); - VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc)); + next_pcs.push_back (MAKE_THUMB_ADDR (pc)); return next_pcs; } @@ -393,8 +395,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) { /* Advance to the next instruction. All the 32-bit instructions share a common prefix. */ - VEC_safe_push (CORE_ADDR, next_pcs, - MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1))); + next_pcs.push_back (MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1))); } return next_pcs; @@ -628,7 +629,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) nextpc = pc_val + imm; } - VEC_safe_push (CORE_ADDR, next_pcs, nextpc); + next_pcs.push_back (nextpc); return next_pcs; } @@ -641,7 +642,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self) in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory address in GDB and arm_addr_bits_remove in GDBServer. */ -static VEC (CORE_ADDR) * +static std::vector arm_get_next_pcs_raw (struct arm_get_next_pcs *self) { int byte_order = self->byte_order; @@ -652,7 +653,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self) CORE_ADDR nextpc; struct regcache *regcache = self->regcache; CORE_ADDR pc = regcache_read_pc (self->regcache); - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; pc_val = (unsigned long) pc; this_instr = self->ops->read_mem_uint (pc, 4, byte_order_for_code); @@ -709,7 +710,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self) ? (pc_val + 8) : regcache_raw_get_unsigned (regcache, rn)); - VEC_safe_push (CORE_ADDR, next_pcs, nextpc); + next_pcs.push_back (nextpc); return next_pcs; } @@ -899,40 +900,36 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self) } } - VEC_safe_push (CORE_ADDR, next_pcs, nextpc); + next_pcs.push_back (nextpc); + return next_pcs; } /* See arm-get-next-pcs.h. */ -VEC (CORE_ADDR) * +std::vector arm_get_next_pcs (struct arm_get_next_pcs *self) { - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; if (self->ops->is_thumb (self)) { next_pcs = thumb_deal_with_atomic_sequence_raw (self); - if (next_pcs == NULL) + if (next_pcs.empty ()) next_pcs = thumb_get_next_pcs_raw (self); } else { next_pcs = arm_deal_with_atomic_sequence_raw (self); - if (next_pcs == NULL) + if (next_pcs.empty ()) next_pcs = arm_get_next_pcs_raw (self); } if (self->ops->fixup != NULL) { - CORE_ADDR nextpc; - int i; - - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, nextpc); i++) - { - nextpc = self->ops->fixup (self, nextpc); - VEC_replace (CORE_ADDR, next_pcs, i, nextpc); - } + for (CORE_ADDR &pc_ref : next_pcs) + pc_ref = self->ops->fixup (self, pc_ref); } + return next_pcs; } diff --git a/gdb/arch/arm-get-next-pcs.h b/gdb/arch/arm-get-next-pcs.h index 2300ac1d7b..c6723be838 100644 --- a/gdb/arch/arm-get-next-pcs.h +++ b/gdb/arch/arm-get-next-pcs.h @@ -19,7 +19,8 @@ #ifndef ARM_GET_NEXT_PCS_H #define ARM_GET_NEXT_PCS_H 1 -#include "gdb_vecs.h" + +#include /* Forward declaration. */ struct arm_get_next_pcs; @@ -61,6 +62,6 @@ void arm_get_next_pcs_ctor (struct arm_get_next_pcs *self, struct regcache *regcache); /* Find the next possible PCs after the current instruction executes. */ -VEC (CORE_ADDR) *arm_get_next_pcs (struct arm_get_next_pcs *self); +std::vector arm_get_next_pcs (struct arm_get_next_pcs *self); #endif /* ARM_GET_NEXT_PCS_H */ diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c index e1eab209df..094ed72757 100644 --- a/gdb/arm-linux-tdep.c +++ b/gdb/arm-linux-tdep.c @@ -921,22 +921,16 @@ arm_linux_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self) /* Insert a single step breakpoint at the next executed instruction. */ -static VEC (CORE_ADDR) * +static std::vector arm_linux_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); struct arm_get_next_pcs next_pcs_ctx; - CORE_ADDR pc; - int i; - VEC (CORE_ADDR) *next_pcs = NULL; - struct cleanup *old_chain; /* If the target does have hardware single step, GDB doesn't have to bother software single step. */ if (target_can_do_single_step () == 1) - return NULL; - - old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); + return {}; arm_get_next_pcs_ctor (&next_pcs_ctx, &arm_linux_get_next_pcs_ops, @@ -945,15 +939,10 @@ arm_linux_software_single_step (struct regcache *regcache) 1, regcache); - next_pcs = arm_get_next_pcs (&next_pcs_ctx); - - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) - { - pc = gdbarch_addr_bits_remove (gdbarch, pc); - VEC_replace (CORE_ADDR, next_pcs, i, pc); - } + std::vector next_pcs = arm_get_next_pcs (&next_pcs_ctx); - discard_cleanups (old_chain); + for (CORE_ADDR &pc_ref : next_pcs) + pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); return next_pcs; } diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index c8fabfb31e..24b575be17 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -6295,15 +6295,11 @@ arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self) single-step support. We find the target of the coming instructions and breakpoint them. */ -VEC (CORE_ADDR) * +std::vector arm_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); struct arm_get_next_pcs next_pcs_ctx; - CORE_ADDR pc; - int i; - VEC (CORE_ADDR) *next_pcs = NULL; - struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); arm_get_next_pcs_ctor (&next_pcs_ctx, &arm_get_next_pcs_ops, @@ -6312,15 +6308,10 @@ arm_software_single_step (struct regcache *regcache) 0, regcache); - next_pcs = arm_get_next_pcs (&next_pcs_ctx); - - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) - { - pc = gdbarch_addr_bits_remove (gdbarch, pc); - VEC_replace (CORE_ADDR, next_pcs, i, pc); - } + std::vector next_pcs = arm_get_next_pcs (&next_pcs_ctx); - discard_cleanups (old_chain); + for (CORE_ADDR &pc_ref : next_pcs) + pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref); return next_pcs; } @@ -7898,11 +7889,6 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0) { struct arm_get_next_pcs next_pcs_ctx; - CORE_ADDR pc; - int i; - VEC (CORE_ADDR) *next_pcs = NULL; - struct cleanup *old_chain - = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); arm_get_next_pcs_ctor (&next_pcs_ctx, &arm_get_next_pcs_ops, @@ -7911,17 +7897,15 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, 0, regcache); - next_pcs = arm_get_next_pcs (&next_pcs_ctx); + std::vector next_pcs = arm_get_next_pcs (&next_pcs_ctx); /* If MEMADDR is the next instruction of current pc, do the software single step computation, and get the thumb mode by the destination address. */ - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) + for (CORE_ADDR pc : next_pcs) { if (UNMAKE_THUMB_ADDR (pc) == *pcptr) { - do_cleanups (old_chain); - if (IS_THUMB_ADDR (pc)) { *pcptr = MAKE_THUMB_ADDR (*pcptr); @@ -7931,8 +7915,6 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch, return ARM_BP_KIND_ARM; } } - - do_cleanups (old_chain); } return arm_breakpoint_kind_from_pc (gdbarch, pcptr); diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 8125226362..132978235b 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -29,6 +29,8 @@ struct gdb_get_next_pcs; #include "arch/arm.h" +#include + /* Say how long FP registers are. Used for documentation purposes and code readability in this header. IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ @@ -259,7 +261,7 @@ CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self, int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self); -VEC (CORE_ADDR) *arm_software_single_step (struct regcache *); +std::vector arm_software_single_step (struct regcache *); int arm_is_thumb (struct regcache *regcache); int arm_frame_is_thumb (struct frame_info *frame); diff --git a/gdb/breakpoint.c b/gdb/breakpoint.c index 4940ec271b..ba974c8cf0 100644 --- a/gdb/breakpoint.c +++ b/gdb/breakpoint.c @@ -15114,22 +15114,18 @@ int insert_single_step_breakpoints (struct gdbarch *gdbarch) { struct regcache *regcache = get_current_regcache (); - VEC (CORE_ADDR) * next_pcs; + std::vector next_pcs; next_pcs = gdbarch_software_single_step (gdbarch, regcache); - if (next_pcs != NULL) + if (!next_pcs.empty ()) { - int i; - CORE_ADDR pc; struct frame_info *frame = get_current_frame (); struct address_space *aspace = get_frame_address_space (frame); - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++) + for (CORE_ADDR pc : next_pcs) insert_single_step_breakpoint (gdbarch, aspace, pc); - VEC_free (CORE_ADDR, next_pcs); - return 1; } else diff --git a/gdb/cris-tdep.c b/gdb/cris-tdep.c index a46356ff8b..eb397725a7 100644 --- a/gdb/cris-tdep.c +++ b/gdb/cris-tdep.c @@ -2060,12 +2060,12 @@ find_step_target (struct regcache *regcache, inst_env_type *inst_env) digs through the opcodes in order to find all possible targets. Either one ordinary target or two targets for branches may be found. */ -static VEC (CORE_ADDR) * +static std::vector cris_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); inst_env_type inst_env; - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; /* Analyse the present instruction environment and insert breakpoints. */ @@ -2083,14 +2083,14 @@ cris_software_single_step (struct regcache *regcache) CORE_ADDR next_pc = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; - VEC_safe_push (CORE_ADDR, next_pcs, next_pc); + next_pcs.push_back (next_pc); if (inst_env.branch_found && (CORE_ADDR) inst_env.branch_break_address != next_pc) { CORE_ADDR branch_target_address = (CORE_ADDR) inst_env.branch_break_address; - VEC_safe_push (CORE_ADDR, next_pcs, branch_target_address); + next_pcs.push_back (branch_target_address); } } diff --git a/gdb/gdbarch.c b/gdb/gdbarch.c index 56643256da..f085c36deb 100644 --- a/gdb/gdbarch.c +++ b/gdb/gdbarch.c @@ -3223,7 +3223,7 @@ gdbarch_software_single_step_p (struct gdbarch *gdbarch) return gdbarch->software_single_step != NULL; } -VEC (CORE_ADDR) * +std::vector gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache) { gdb_assert (gdbarch != NULL); diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h index 7168e34b9b..2eed6b5b6d 100644 --- a/gdb/gdbarch.h +++ b/gdb/gdbarch.h @@ -35,6 +35,7 @@ #ifndef GDBARCH_H #define GDBARCH_H +#include #include "frame.h" #include "dis-asm.h" @@ -700,8 +701,8 @@ extern void set_gdbarch_addr_bits_remove (struct gdbarch *gdbarch, gdbarch_addr_ extern int gdbarch_software_single_step_p (struct gdbarch *gdbarch); -typedef VEC (CORE_ADDR) * (gdbarch_software_single_step_ftype) (struct regcache *regcache); -extern VEC (CORE_ADDR) * gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache); +typedef std::vector (gdbarch_software_single_step_ftype) (struct regcache *regcache); +extern std::vector gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache); extern void set_gdbarch_software_single_step (struct gdbarch *gdbarch, gdbarch_software_single_step_ftype *software_single_step); /* Return non-zero if the processor is executing a delay slot and a diff --git a/gdb/gdbarch.sh b/gdb/gdbarch.sh index 31bee666b6..b91dc9c12e 100755 --- a/gdb/gdbarch.sh +++ b/gdb/gdbarch.sh @@ -640,7 +640,7 @@ m;CORE_ADDR;addr_bits_remove;CORE_ADDR addr;addr;;core_addr_identity;;0 # the condition and only put the breakpoint at the branch destination if # the condition is true, so that we ensure forward progress when stepping # past a conditional branch to self. -F;VEC (CORE_ADDR) *;software_single_step;struct regcache *regcache;regcache +F;std::vector;software_single_step;struct regcache *regcache;regcache # Return non-zero if the processor is executing a delay slot and a # further single-step is needed before the instruction finishes. @@ -1268,6 +1268,7 @@ cat < #include "frame.h" #include "dis-asm.h" diff --git a/gdb/gdbserver/linux-arm-low.c b/gdb/gdbserver/linux-arm-low.c index fc2b34870a..5a3f465dee 100644 --- a/gdb/gdbserver/linux-arm-low.c +++ b/gdb/gdbserver/linux-arm-low.c @@ -925,11 +925,10 @@ arm_arch_setup (void) /* Fetch the next possible PCs after the current instruction executes. */ -static VEC (CORE_ADDR) * +static std::vector arm_gdbserver_get_next_pcs (struct regcache *regcache) { struct arm_get_next_pcs next_pcs_ctx; - VEC (CORE_ADDR) *next_pcs = NULL; arm_get_next_pcs_ctor (&next_pcs_ctx, &get_next_pcs_ops, @@ -939,9 +938,7 @@ arm_gdbserver_get_next_pcs (struct regcache *regcache) 1, regcache); - next_pcs = arm_get_next_pcs (&next_pcs_ctx); - - return next_pcs; + return arm_get_next_pcs (&next_pcs_ctx); } /* Support for hardware single step. */ diff --git a/gdb/gdbserver/linux-low.c b/gdb/gdbserver/linux-low.c index e27cbf825a..ea3c81b847 100644 --- a/gdb/gdbserver/linux-low.c +++ b/gdb/gdbserver/linux-low.c @@ -4317,19 +4317,14 @@ enqueue_pending_signal (struct lwp_info *lwp, int signal, siginfo_t *info) static void install_software_single_step_breakpoints (struct lwp_info *lwp) { - int i; - CORE_ADDR pc; struct thread_info *thread = get_lwp_thread (lwp); struct regcache *regcache = get_thread_regcache (thread, 1); - VEC (CORE_ADDR) *next_pcs = NULL; struct cleanup *old_chain = make_cleanup_restore_current_thread (); - make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs); - current_thread = thread; - next_pcs = (*the_low_target.get_next_pcs) (regcache); + std::vector next_pcs = the_low_target.get_next_pcs (regcache); - for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); ++i) + for (CORE_ADDR pc : next_pcs) set_single_step_breakpoint (pc, current_ptid); do_cleanups (old_chain); diff --git a/gdb/gdbserver/linux-low.h b/gdb/gdbserver/linux-low.h index 7dcbfcfca4..6328da03ed 100644 --- a/gdb/gdbserver/linux-low.h +++ b/gdb/gdbserver/linux-low.h @@ -154,7 +154,7 @@ struct linux_target_ops const gdb_byte *(*sw_breakpoint_from_kind) (int kind, int *size); /* Find the next possible PCs after the current instruction executes. */ - VEC (CORE_ADDR) *(*get_next_pcs) (struct regcache *regcache); + std::vector (*get_next_pcs) (struct regcache *regcache); int decr_pc_after_break; int (*breakpoint_at) (CORE_ADDR pc); diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 45d1d731b0..d38cc225dd 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -3879,7 +3879,7 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) #define SC_OPCODE 0x38 #define SCD_OPCODE 0x3c -static VEC (CORE_ADDR) * +static std::vector mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { CORE_ADDR breaks[2] = {-1, -1}; @@ -3890,12 +3890,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) int index; int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ - VEC (CORE_ADDR) *next_pcs = NULL; insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); /* Assume all atomic sequences start with a ll/lld instruction. */ if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) - return NULL; + return {}; /* Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ @@ -3912,7 +3911,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { case 0: /* SPECIAL */ if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ - return 0; /* fallback to the standard single-step code. */ + return {}; /* fallback to the standard single-step code. */ break; case 1: /* REGIMM */ is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ @@ -3921,7 +3920,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) break; case 2: /* J */ case 3: /* JAL */ - return 0; /* fallback to the standard single-step code. */ + return {}; /* fallback to the standard single-step code. */ case 4: /* BEQ */ case 5: /* BNE */ case 6: /* BLEZ */ @@ -3947,8 +3946,8 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { branch_bp = loc + mips32_relative_offset (insn) + 4; if (last_breakpoint >= 1) - return 0; /* More than one branch found, fallback to the - standard single-step code. */ + return {}; /* More than one branch found, fallback to the + standard single-step code. */ breaks[1] = branch_bp; last_breakpoint++; } @@ -3959,7 +3958,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) /* Assume that the atomic sequence ends with a sc/scd instruction. */ if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) - return NULL; + return {}; loc += MIPS_INSN32_SIZE; @@ -3971,14 +3970,16 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) last_breakpoint = 0; + std::vector next_pcs; + /* Effectively inserts the breakpoints. */ for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } -static VEC (CORE_ADDR) * +static std::vector micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { @@ -3992,17 +3993,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, ULONGEST insn; int insn_count; int index; - VEC (CORE_ADDR) *next_pcs = NULL; /* Assume all atomic sequences start with a ll/lld instruction. */ insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ - return NULL; + return {}; loc += MIPS_INSN16_SIZE; insn <<= 16; insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ - return NULL; + return {}; loc += MIPS_INSN16_SIZE; /* Assume all atomic sequences end with an sc/scd instruction. Assume @@ -4072,7 +4072,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, case 0x35: /* J: bits 110101 */ case 0x3d: /* JAL: bits 111101 */ case 0x3c: /* JALX: bits 111100 */ - return 0; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ case 0x18: /* POOL32C: bits 011000 */ if ((b12s4_op (insn) & 0xb) == 0xb) @@ -4099,24 +4099,24 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, && b5s5_op (insn) != 0x18) /* JRADDIUSP: bits 010001 11000 */ break; - return NULL; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ case 0x33: /* B16: bits 110011 */ - return NULL; /* Fall back to the standard single-step code. */ + return {}; /* Fall back to the standard single-step code. */ } break; } if (is_branch) { if (last_breakpoint >= 1) - return NULL; /* More than one branch found, fallback to the - standard single-step code. */ + return {}; /* More than one branch found, fallback to the + standard single-step code. */ breaks[1] = branch_bp; last_breakpoint++; } } if (!sc_found) - return NULL; + return {}; /* Insert a breakpoint right after the end of the atomic sequence. */ breaks[0] = loc; @@ -4126,14 +4126,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) last_breakpoint = 0; + std::vector next_pcs; + /* Effectively inserts the breakpoints. */ for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } -static VEC (CORE_ADDR) * +static std::vector deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { if (mips_pc_is_mips (pc)) @@ -4141,7 +4143,7 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) else if (mips_pc_is_micromips (gdbarch, pc)) return micromips_deal_with_atomic_sequence (gdbarch, pc); else - return NULL; + return {}; } /* mips_software_single_step() is called just before we want to resume @@ -4149,22 +4151,21 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) or kernel single-step support (MIPS on GNU/Linux for example). We find the target of the coming instruction and breakpoint it. */ -VEC (CORE_ADDR) * +std::vector mips_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); CORE_ADDR pc, next_pc; - VEC (CORE_ADDR) *next_pcs; pc = regcache_read_pc (regcache); - next_pcs = deal_with_atomic_sequence (gdbarch, pc); - if (next_pcs != NULL) + std::vector next_pcs = deal_with_atomic_sequence (gdbarch, pc); + + if (!next_pcs.empty ()) return next_pcs; next_pc = mips_next_pc (regcache, pc); - VEC_safe_push (CORE_ADDR, next_pcs, next_pc); - return next_pcs; + return {next_pc}; } /* Test whether the PC points to the return instruction at the diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h index ce168cc49c..541a275f30 100644 --- a/gdb/mips-tdep.h +++ b/gdb/mips-tdep.h @@ -154,7 +154,8 @@ enum }; /* Single step based on where the current instruction will take us. */ -extern VEC (CORE_ADDR) *mips_software_single_step (struct regcache *regcache); +extern std::vector mips_software_single_step + (struct regcache *regcache); /* Strip the ISA (compression) bit off from ADDR. */ extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr); diff --git a/gdb/moxie-tdep.c b/gdb/moxie-tdep.c index dd7a6f4bfb..2972d5248e 100644 --- a/gdb/moxie-tdep.c +++ b/gdb/moxie-tdep.c @@ -299,7 +299,7 @@ moxie_process_readu (CORE_ADDR addr, gdb_byte *buf, /* Insert a single step breakpoint. */ -static VEC (CORE_ADDR) * +static std::vector moxie_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -309,7 +309,7 @@ moxie_software_single_step (struct regcache *regcache) uint32_t tmpu32; ULONGEST fp; enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; addr = regcache_read_pc (regcache); @@ -337,9 +337,8 @@ moxie_software_single_step (struct regcache *regcache) case 0x09: /* bleu */ /* Insert breaks on both branches, because we can't currently tell which way things will go. */ - VEC_safe_push (CORE_ADDR, next_pcs, addr + 2); - VEC_safe_push (CORE_ADDR, next_pcs, - addr + 2 + INST2OFFSET(inst)); + next_pcs.push_back (addr + 2); + next_pcs.push_back (addr + 2 + INST2OFFSET(inst)); break; default: { @@ -351,7 +350,7 @@ moxie_software_single_step (struct regcache *regcache) else { /* This is a Form 2 instruction. They are all 16 bits. */ - VEC_safe_push (CORE_ADDR, next_pcs, addr + 2); + next_pcs.push_back (addr + 2); } } else @@ -398,7 +397,7 @@ moxie_software_single_step (struct regcache *regcache) case 0x32: /* udiv.l */ case 0x33: /* mod.l */ case 0x34: /* umod.l */ - VEC_safe_push (CORE_ADDR, next_pcs, addr + 2); + next_pcs.push_back (addr + 2); break; /* 32-bit instructions. */ @@ -408,7 +407,7 @@ moxie_software_single_step (struct regcache *regcache) case 0x37: /* sto.b */ case 0x38: /* ldo.s */ case 0x39: /* sto.s */ - VEC_safe_push (CORE_ADDR, next_pcs, addr + 4); + next_pcs.push_back (addr + 4); break; /* 48-bit instructions. */ @@ -421,27 +420,26 @@ moxie_software_single_step (struct regcache *regcache) case 0x20: /* ldi.s (immediate) */ case 0x22: /* lda.s */ case 0x24: /* sta.s */ - VEC_safe_push (CORE_ADDR, next_pcs, addr + 6); + next_pcs.push_back (addr + 6); break; /* Control flow instructions. */ case 0x03: /* jsra */ case 0x1a: /* jmpa */ - VEC_safe_push (CORE_ADDR, next_pcs, - moxie_process_readu (addr + 2, buf, 4, byte_order)); + next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4, + byte_order)); break; case 0x04: /* ret */ regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp); - VEC_safe_push (CORE_ADDR, next_pcs, - moxie_process_readu (fp + 4, buf, 4, byte_order)); + next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order)); break; case 0x19: /* jsr */ case 0x25: /* jmp */ regcache_raw_read (regcache, (inst >> 4) & 0xf, (gdb_byte *) & tmpu32); - VEC_safe_push (CORE_ADDR, next_pcs, tmpu32); + next_pcs.push_back (tmpu32); break; case 0x30: /* swi */ diff --git a/gdb/nios2-tdep.c b/gdb/nios2-tdep.c index 3d39451804..c214078921 100644 --- a/gdb/nios2-tdep.c +++ b/gdb/nios2-tdep.c @@ -2219,16 +2219,13 @@ nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc) /* Implement the software_single_step gdbarch method. */ -static VEC (CORE_ADDR) * +static std::vector nios2_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache)); - VEC (CORE_ADDR) *next_pcs = NULL; - VEC_safe_push (CORE_ADDR, next_pcs, next_pc); - - return next_pcs; + return {next_pc}; } /* Implement the get_longjump_target gdbarch method. */ diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h index 875ad93b18..8d15ace214 100644 --- a/gdb/ppc-tdep.h +++ b/gdb/ppc-tdep.h @@ -76,7 +76,8 @@ int ppc_altivec_support_p (struct gdbarch *gdbarch); /* Return non-zero if the architecture described by GDBARCH has VSX registers (vsr0 --- vsr63). */ int vsx_support_p (struct gdbarch *gdbarch); -VEC (CORE_ADDR) *ppc_deal_with_atomic_sequence (struct regcache *regcache); +std::vector ppc_deal_with_atomic_sequence + (struct regcache *regcache); /* Register set description. */ diff --git a/gdb/rs6000-aix-tdep.c b/gdb/rs6000-aix-tdep.c index a14e93c66a..7d817bee1d 100644 --- a/gdb/rs6000-aix-tdep.c +++ b/gdb/rs6000-aix-tdep.c @@ -673,7 +673,7 @@ branch_dest (struct regcache *regcache, int opcode, int instr, /* AIX does not support PT_STEP. Simulate it. */ -static VEC (CORE_ADDR) * +static std::vector rs6000_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -682,14 +682,13 @@ rs6000_software_single_step (struct regcache *regcache) CORE_ADDR loc; CORE_ADDR breaks[2]; int opcode; - VEC (CORE_ADDR) *next_pcs; loc = regcache_read_pc (regcache); insn = read_memory_integer (loc, 4, byte_order); - next_pcs = ppc_deal_with_atomic_sequence (regcache); - if (next_pcs != NULL) + std::vector next_pcs = ppc_deal_with_atomic_sequence (regcache); + if (!next_pcs.empty ()) return next_pcs; breaks[0] = loc + PPC_INSN_SIZE; @@ -705,7 +704,8 @@ rs6000_software_single_step (struct regcache *regcache) /* ignore invalid breakpoint. */ if (breaks[ii] == -1) continue; - VEC_safe_push (CORE_ADDR, next_pcs, breaks[ii]); + + next_pcs.push_back (breaks[ii]); } errno = 0; /* FIXME, don't ignore errors! */ diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c index eb784c562f..4072464558 100644 --- a/gdb/rs6000-tdep.c +++ b/gdb/rs6000-tdep.c @@ -1165,7 +1165,7 @@ ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch, Load And Reserve instruction and ending with a Store Conditional instruction. If such a sequence is found, attempt to step through it. A breakpoint is placed at the end of the sequence. */ -VEC (CORE_ADDR) * +std::vector ppc_deal_with_atomic_sequence (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -1180,11 +1180,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ int bc_insn_count = 0; /* Conditional branch instruction count. */ - VEC (CORE_ADDR) *next_pcs = NULL; /* Assume all atomic sequences start with a Load And Reserve instruction. */ if (!IS_LOAD_AND_RESERVE_INSN (insn)) - return NULL; + return {}; /* Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ @@ -1202,8 +1201,8 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) int absolute = insn & 2; if (bc_insn_count >= 1) - return 0; /* More than one conditional branch found, fallback - to the standard single-step code. */ + return {}; /* More than one conditional branch found, fallback + to the standard single-step code. */ if (absolute) breaks[1] = immediate; @@ -1221,7 +1220,7 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) /* Assume that the atomic sequence ends with a Store Conditional instruction. */ if (!IS_STORE_CONDITIONAL_INSN (insn)) - return NULL; + return {}; closing_insn = loc; loc += PPC_INSN_SIZE; @@ -1237,8 +1236,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache) || (breaks[1] >= pc && breaks[1] <= closing_insn))) last_breakpoint = 0; + std::vector next_pcs; + for (index = 0; index <= last_breakpoint; index++) - VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]); + next_pcs.push_back (breaks[index]); return next_pcs; } diff --git a/gdb/s390-linux-tdep.c b/gdb/s390-linux-tdep.c index 55129d81f4..8139d817d9 100644 --- a/gdb/s390-linux-tdep.c +++ b/gdb/s390-linux-tdep.c @@ -725,7 +725,7 @@ s390_is_partial_instruction (struct gdbarch *gdbarch, CORE_ADDR loc, int *len) process about 4kiB of it each time, leading to O(n**2) memory and time complexity. */ -static VEC (CORE_ADDR) * +static std::vector s390_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -733,33 +733,30 @@ s390_software_single_step (struct regcache *regcache) enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int len; uint16_t insn; - VEC (CORE_ADDR) *next_pcs = NULL; /* Special handling only if recording. */ if (!record_full_is_used ()) - return NULL; + return {}; /* First, match a partial instruction. */ if (!s390_is_partial_instruction (gdbarch, loc, &len)) - return NULL; + return {}; loc += len; /* Second, look for a branch back to it. */ insn = read_memory_integer (loc, 2, byte_order); if (insn != 0xa714) /* BRC with mask 1 */ - return NULL; + return {}; insn = read_memory_integer (loc + 2, 2, byte_order); if (insn != (uint16_t) -(len / 2)) - return NULL; + return {}; loc += 4; /* Found it, step past the whole thing. */ - VEC_safe_push (CORE_ADDR, next_pcs, loc); - - return next_pcs; + return {loc}; } static int diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c index 078907a5d4..14d9fc97bc 100644 --- a/gdb/sparc-tdep.c +++ b/gdb/sparc-tdep.c @@ -1643,7 +1643,7 @@ sparc_step_trap (struct frame_info *frame, unsigned long insn) return 0; } -static VEC (CORE_ADDR) * +static std::vector sparc_software_single_step (struct regcache *regcache) { struct gdbarch *arch = get_regcache_arch (regcache); @@ -1651,7 +1651,7 @@ sparc_software_single_step (struct regcache *regcache) CORE_ADDR npc, nnpc; CORE_ADDR pc, orig_npc; - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum); orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum); @@ -1659,10 +1659,10 @@ sparc_software_single_step (struct regcache *regcache) /* Analyze the instruction at PC. */ nnpc = sparc_analyze_control_transfer (regcache, pc, &npc); if (npc != 0) - VEC_safe_push (CORE_ADDR, next_pcs, npc); + next_pcs.push_back (npc); if (nnpc != 0) - VEC_safe_push (CORE_ADDR, next_pcs, nnpc); + next_pcs.push_back (nnpc); /* Assert that we have set at least one breakpoint, and that they're not set at the same spot - unless we're going diff --git a/gdb/spu-tdep.c b/gdb/spu-tdep.c index 91b1a0e4d6..08ab19418f 100644 --- a/gdb/spu-tdep.c +++ b/gdb/spu-tdep.c @@ -1612,7 +1612,7 @@ spu_memory_remove_breakpoint (struct gdbarch *gdbarch, /* Software single-stepping support. */ -static VEC (CORE_ADDR) * +static std::vector spu_software_single_step (struct regcache *regcache) { struct gdbarch *gdbarch = get_regcache_arch (regcache); @@ -1622,7 +1622,7 @@ spu_software_single_step (struct regcache *regcache) int offset, reg; gdb_byte buf[4]; ULONGEST lslr; - VEC (CORE_ADDR) *next_pcs = NULL; + std::vector next_pcs; pc = regcache_read_pc (regcache); @@ -1645,7 +1645,7 @@ spu_software_single_step (struct regcache *regcache) else next_pc = (SPUADDR_ADDR (pc) + 4) & lslr; - VEC_safe_push (CORE_ADDR, next_pcs, SPUADDR (SPUADDR_SPU (pc), next_pc)); + next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc)); if (is_branch (insn, &offset, ®)) { @@ -1658,8 +1658,7 @@ spu_software_single_step (struct regcache *regcache) target = target & lslr; if (target != next_pc) - VEC_safe_push (CORE_ADDR, next_pcs, SPUADDR (SPUADDR_SPU (pc), - target)); + next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target)); } return next_pcs; diff --git a/gdb/tic6x-tdep.c b/gdb/tic6x-tdep.c index 23b7b280f6..012b749389 100644 --- a/gdb/tic6x-tdep.c +++ b/gdb/tic6x-tdep.c @@ -699,15 +699,12 @@ tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc) /* This is the implementation of gdbarch method software_single_step. */ -static VEC (CORE_ADDR) * +static std::vector tic6x_software_single_step (struct regcache *regcache) { CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache)); - VEC (CORE_ADDR) *next_pcs = NULL; - VEC_safe_push (CORE_ADDR, next_pcs, next_pc); - - return next_pcs; + return {next_pc}; } /* This is the implementation of gdbarch method frame_align. */