From patchwork Sat Mar 11 17:03:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 19536 Received: (qmail 105971 invoked by alias); 11 Mar 2017 17:16:59 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 105950 invoked by uid 89); 11 Mar 2017 17:16:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-24.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy= X-HELO: barracuda.ebox.ca Received: from barracuda.ebox.ca (HELO barracuda.ebox.ca) (96.127.255.19) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 11 Mar 2017 17:16:58 +0000 X-ASG-Debug-ID: 1489251835-0c856e65d5183e770001-fS2M51 Received: from smtp.electronicbox.net (smtp.electronicbox.net [96.127.255.82]) by barracuda.ebox.ca with ESMTP id 0bhSVpj8xktIa7FO (version=TLSv1 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sat, 11 Mar 2017 12:03:55 -0500 (EST) X-Barracuda-Envelope-From: simon.marchi@polymtl.ca X-Barracuda-RBL-Trusted-Forwarder: 96.127.255.82 Received: from simark.lan (173-246-11-162.qc.cable.ebox.net [173.246.11.162]) by smtp.electronicbox.net (Postfix) with ESMTP id AF0DA440E80; Sat, 11 Mar 2017 12:03:55 -0500 (EST) From: Simon Marchi X-Barracuda-Effective-Source-IP: cable-11.246.173-162.electronicbox.net[173.246.11.162] X-Barracuda-Apparent-Source-IP: 173.246.11.162 X-Barracuda-RBL-IP: 173.246.11.162 To: gdb-patches@sourceware.org Cc: Simon Marchi Subject: [PATCH v1.99 4/6] aarc64-linux-nat: Use ptid from regcache instead of inferior_ptid Date: Sat, 11 Mar 2017 12:03:52 -0500 X-ASG-Orig-Subj: [PATCH v1.99 4/6] aarc64-linux-nat: Use ptid from regcache instead of inferior_ptid Message-Id: <20170311170354.18468-5-simon.marchi@polymtl.ca> In-Reply-To: <20170311170354.18468-1-simon.marchi@polymtl.ca> References: <20170311170354.18468-1-simon.marchi@polymtl.ca> X-Barracuda-Connect: smtp.electronicbox.net[96.127.255.82] X-Barracuda-Start-Time: 1489251835 X-Barracuda-Encrypted: DHE-RSA-AES256-SHA X-Barracuda-URL: https://96.127.255.19:443/cgi-mod/mark.cgi X-Barracuda-Scan-Msg-Size: 1839 X-Barracuda-BRTS-Status: 1 X-Barracuda-Spam-Score: 0.00 X-Barracuda-Spam-Status: No, SCORE=0.00 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=8.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.37151 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- X-IsSubscribed: yes gdb/ChangeLog: * aarch64-linux-nat.c (fetch_gregs_from_thread, store_gregs_to_thread, fetch_fpregs_from_thread, store_fpregs_to_thread): Use regcache->ptid instead of inferior_ptid. --- gdb/aarch64-linux-nat.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gdb/aarch64-linux-nat.c b/gdb/aarch64-linux-nat.c index 0d472e2e53..3f5b30eaeb 100644 --- a/gdb/aarch64-linux-nat.c +++ b/gdb/aarch64-linux-nat.c @@ -163,7 +163,7 @@ fetch_gregs_from_thread (struct regcache *regcache) and arm. */ gdb_static_assert (sizeof (regs) >= 18 * 4); - tid = ptid_get_lwp (inferior_ptid); + tid = ptid_get_lwp (regcache_get_ptid (regcache)); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) @@ -200,7 +200,7 @@ store_gregs_to_thread (const struct regcache *regcache) /* Make sure REGS can hold all registers contents on both aarch64 and arm. */ gdb_static_assert (sizeof (regs) >= 18 * 4); - tid = ptid_get_lwp (inferior_ptid); + tid = ptid_get_lwp (regcache_get_ptid (regcache)); iovec.iov_base = ®s; if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) @@ -244,7 +244,7 @@ fetch_fpregs_from_thread (struct regcache *regcache) and arm. */ gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); - tid = ptid_get_lwp (inferior_ptid); + tid = ptid_get_lwp (regcache_get_ptid (regcache)); iovec.iov_base = ®s; @@ -291,7 +291,7 @@ store_fpregs_to_thread (const struct regcache *regcache) /* Make sure REGS can hold all VFP registers contents on both aarch64 and arm. */ gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); - tid = ptid_get_lwp (inferior_ptid); + tid = ptid_get_lwp (regcache_get_ptid (regcache)); iovec.iov_base = ®s;