From patchwork Tue Feb 14 10:01:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anton Kolesov X-Patchwork-Id: 19248 Received: (qmail 97810 invoked by alias); 14 Feb 2017 10:01:48 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 97771 invoked by uid 89); 14 Feb 2017 10:01:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.7 required=5.0 tests=AWL, BAYES_50, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=H*RU:sk:smtprel, Hx-spam-relays-external:sk:smtprel, HX-HELO:sk:smtprel, descriptions X-HELO: smtprelay.synopsys.com Received: from smtprelay.synopsys.com (HELO smtprelay.synopsys.com) (198.182.60.111) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 14 Feb 2017 10:01:36 +0000 Received: from mailhost.synopsys.com (mailhost2.synopsys.com [10.13.184.66]) by smtprelay.synopsys.com (Postfix) with ESMTP id 67DD310C0EBD for ; Tue, 14 Feb 2017 02:01:35 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 52EDD1E7; Tue, 14 Feb 2017 02:01:35 -0800 (PST) Received: from akolesov-lab.internal.synopsys.com (akolesov-lab.internal.synopsys.com [10.121.8.134]) by mailhost.synopsys.com (Postfix) with ESMTP id 581611B8; Tue, 14 Feb 2017 02:01:34 -0800 (PST) From: Anton Kolesov To: gdb-patches@sourceware.org Cc: Anton Kolesov , Francois Bedard Subject: [PATCH 1/5] arc: Align internal regnums with architectural regnums Date: Tue, 14 Feb 2017 13:01:26 +0300 Message-Id: <20170214100130.29194-1-Anton.Kolesov@synopsys.com> Add ARC_LIMM_REGNUM to arc_regnum enumeration and assign a number 62 to it. This ensures that for core registers internal register numbers in this enum are the same as architectural numbers. This allows to use internal register numbers in the contexts where architectural number is implied, for example when disassembling instruction during prologue analysis. gdb/ChangeLog: yyyy-mm-dd Anton Kolesov * arc-tdep.c (core_v2_register_names, core_arcompact_register_names) Add "limm" and "reserved". (arc_cannot_fetch_register, arc_cannot_store_register): Add ARC_RESERVED_REGNUM and ARC_LIMM_REGNUM. * arc-tdep.h (arc_regnum): Likewise. --- gdb/arc-tdep.c | 28 +++++++++++++++++++++------- gdb/arc-tdep.h | 16 ++++++++++++++++ 2 files changed, 37 insertions(+), 7 deletions(-) diff --git a/gdb/arc-tdep.c b/gdb/arc-tdep.c index 0800d7b..f78e3a9 100644 --- a/gdb/arc-tdep.c +++ b/gdb/arc-tdep.c @@ -86,7 +86,7 @@ static const char *const core_v2_register_names[] = { "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "accl", "acch", - "lp_count", "pcl", + "lp_count", "reserved", "limm", "pcl", }; static const char *const aux_minimal_register_names[] = { @@ -109,7 +109,7 @@ static const char *const core_arcompact_register_names[] = { "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", "r56", "r57", "r58", "r59", - "lp_count", "pcl", + "lp_count", "reserved", "limm", "pcl", }; /* Implement the "write_pc" gdbarch method. @@ -430,8 +430,19 @@ arc_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, static int arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum) { - /* Assume that register is readable if it is unknown. */ - return FALSE; + /* Assume that register is readable if it is unknown. LIMM and RESERVED are + not real registers, but specific register numbers. They are available as + regnums to align architectural register numbers with GDB internal regnums, + but they shouldn't appear in target descriptions generated by + GDB-servers. */ + switch (regnum) + { + case ARC_RESERVED_REGNUM: + case ARC_LIMM_REGNUM: + return true; + default: + return false; + } } /* Implement the "cannot_store_register" gdbarch method. */ @@ -439,13 +450,16 @@ arc_cannot_fetch_register (struct gdbarch *gdbarch, int regnum) static int arc_cannot_store_register (struct gdbarch *gdbarch, int regnum) { - /* Assume that register is writable if it is unknown. */ + /* Assume that register is writable if it is unknown. See comment in + arc_cannot_fetch_register about LIMM and RESERVED. */ switch (regnum) { + case ARC_RESERVED_REGNUM: + case ARC_LIMM_REGNUM: case ARC_PCL_REGNUM: - return TRUE; + return true; default: - return FALSE; + return false; } } diff --git a/gdb/arc-tdep.h b/gdb/arc-tdep.h index 422db46..326f486 100644 --- a/gdb/arc-tdep.h +++ b/gdb/arc-tdep.h @@ -24,6 +24,12 @@ /* Need disassemble_info. */ #include "dis-asm.h" +/* To simplify GDB code this enum assumes that internal regnums should be same + as architectural register numbers, i.e. PCL regnum is 63. This allows to + use internal GDB regnums as architectural numbers when dealing with + instruction encodings, for example when analyzing what are the registers + saved in function prologue. */ + enum arc_regnum { /* Core registers. */ @@ -49,6 +55,16 @@ enum arc_regnum ARC_BLINK_REGNUM, /* Zero-delay loop counter. */ ARC_LP_COUNT_REGNUM = 60, + /* Reserved register number. There should never be a register with such + number, this name is needed only for a sanity check in + arc_cannot_(fetch|store)_register. */ + ARC_RESERVED_REGNUM, + /* Long-immediate value. This is not a physical register - if instruction + has register 62 as an operand, then this operand is a literal value + stored in the instruction memory right after the instruction itself. + This value is required in this enumeration as an architectural number + for instruction analysis. */ + ARC_LIMM_REGNUM, /* Program counter, aligned to 4-bytes, read-only. */ ARC_PCL_REGNUM, ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,