From patchwork Fri Feb 3 19:50:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Ellcey X-Patchwork-Id: 19113 Received: (qmail 55482 invoked by alias); 3 Feb 2017 19:50:57 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 55444 invoked by uid 89); 3 Feb 2017 19:50:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.2 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=2612, 2620, 1512, sheer X-HELO: camailhost.cavium.com Received: from camailhost.cavium.com (HELO camailhost.cavium.com) (12.108.191.230) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 03 Feb 2017 19:50:46 +0000 Received: from sellcey-dt.caveonetworks.com ([10.18.104.136]) by camailhost.cavium.com (8.14.7/8.14.7) with ESMTP id v13Joiu6008212 for ; Fri, 3 Feb 2017 11:50:45 -0800 Received: from sellcey-dt.caveonetworks.com (localhost [127.0.0.1]) by sellcey-dt.caveonetworks.com (8.15.2/8.15.2/Debian-3) with ESMTP id v13JoitZ020913 for ; Fri, 3 Feb 2017 11:50:44 -0800 Received: (from sellcey@localhost) by sellcey-dt.caveonetworks.com (8.15.2/8.15.2/Submit) id v13JoiPq020912; Fri, 3 Feb 2017 11:50:44 -0800 Date: Fri, 3 Feb 2017 11:50:44 -0800 From: Steve Ellcey Message-Id: <201702031950.v13JoiPq020912@sellcey-dt.caveonetworks.com> To: gdb-patches@sourceware.org Subject: [PATCH] aarch64 testsuite patch for ILP32 Reply-To: sellcey@cavium.com While working on aarch64 ILP32 support for gdb I ran into two tests that contain aarch64 inline assembly and that do not work when run in ILP32 mode. I would like to check in this patch even though the ILP32 support is not yet in gdb. That way I can minimize the subsequent patch to support ILP32 mode. This change also fixes a latent bug that is in aarch64-fp.c. The instructions that load q0 and q1 assume the address they want to use is in register x0 but the code does not gaurantee that. It happens to work because we do not optimize the compilation and GCC uses x0 as a temporary register in the earlier statement but that is just sheer luck. I have fixed this by adding a read argument to the load instructions to ensure they have the right value. Tested in ILP32 and LP64 modes on aarch64. OK to checkin? Steve Ellcey sellcey@cavium.com 2017-02-03 Steve Ellcey * gdb.arch/aarch64-atomic-inst.c: Include stdint.h, use uint64_t instead of long for 64 bit types. * gdb.arch/aarch64-fp.c (main): Use %w0 instead of %x0 in 32 bit mode. Specify input register for ldr of q0 and q1. diff --git a/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c b/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c index 4358252..0c1f557 100644 --- a/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c +++ b/gdb/testsuite/gdb.arch/aarch64-atomic-inst.c @@ -15,10 +15,12 @@ You should have received a copy of the GNU General Public License along with this program. If not, see . */ +#include + int main(void) { - unsigned long tmp, cond; - unsigned long dword = 0; + uint64_t tmp, cond; + uint64_t dword = 0; /* Test that we can step over ldxr/stxr. This sequence should step from ldxr to the following __asm __volatile. */ diff --git a/gdb/testsuite/gdb.arch/aarch64-fp.c b/gdb/testsuite/gdb.arch/aarch64-fp.c index 5507de8..6a8f8bc 100644 --- a/gdb/testsuite/gdb.arch/aarch64-fp.c +++ b/gdb/testsuite/gdb.arch/aarch64-fp.c @@ -26,12 +26,20 @@ main (void) void *addr; addr = &buf0[0]; +#if __LP64__ __asm __volatile ("ldr %x0, [%1]" : "=r" (val) : "r" (&addr)); - __asm __volatile ("ldr q0, [x0]"); +#else + __asm __volatile ("ldr %w0, [%1]" : "=r" (val) : "r" (&addr)); +#endif + __asm __volatile ("ldr q0, [%x0]" : : "r" (val)); addr = &buf1[0]; +#if __LP64__ __asm __volatile ("ldr %x0, [%1]" : "=r" (val) : "r" (&addr)); - __asm __volatile ("ldr q1, [x0]"); +#else + __asm __volatile ("ldr %w0, [%1]" : "=r" (val) : "r" (&addr)); +#endif + __asm __volatile ("ldr q1, [%x0]" : : "r" (val)); return 1; }