From patchwork Fri Dec 2 09:42:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 18122 Received: (qmail 7581 invoked by alias); 2 Dec 2016 09:42:44 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 7566 invoked by uid 89); 2 Dec 2016 09:42:43 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f66.google.com Received: from mail-wm0-f66.google.com (HELO mail-wm0-f66.google.com) (74.125.82.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 02 Dec 2016 09:42:33 +0000 Received: by mail-wm0-f66.google.com with SMTP id g23so1817418wme.1 for ; Fri, 02 Dec 2016 01:42:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=1+y5EPJd+fciz67NtYlVjo+aeCrxGWk3v21oet5u6us=; b=fTtS2as+KuQKRz/sSVqALmED9xUNpBphQAbG9XsG8SEjV9gYObMz4ow6eS+hurLRbq vMZMXBCasFMzo0+gKYI7X29yh9C4T0Gzwq35WThMMaigT80yuSOkL5QtuctFDV0q0vS+ jdIciOd6ZQk2aTNUEBFiN7HEG59atoDFHdymkOClTFBPh2a1vu5jWC4ogkR1oKdr6oUF WCFcemGi9aKY4l5zVJxDAkD0iT9TJjsI0aZnRYGHz7Iv8k9uDXuD0illNSodUkSOZZ4N PZo7KTWZ94z7r4+MvU0Q7NLMVAp68PTlX87v9b6/XTeiMsWR0uz0nPSvIyFLBO93lKNt mdZg== X-Gm-Message-State: AKaTC0281x1WPLAkahX18a/1+oxVOqqrws9ahPVX3/CV8blr5P7/h6K2OlOrwIGpFaJYhQ== X-Received: by 10.28.73.135 with SMTP id w129mr1887179wma.42.1480671751105; Fri, 02 Dec 2016 01:42:31 -0800 (PST) Received: from E107787-LIN (gcc1-power7.osuosl.org. [140.211.15.137]) by smtp.gmail.com with ESMTPSA id w18sm2286328wme.9.2016.12.02.01.42.29 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 02 Dec 2016 01:42:30 -0800 (PST) Date: Fri, 2 Dec 2016 09:42:19 +0000 From: Yao Qi To: Pedro Alves Cc: gdb-patches@sourceware.org Subject: Re: [PATCH 2/2 v2] [AArch64] Recognize STR instruction in prologue Message-ID: <20161202094219.GE19289@E107787-LIN> References: <1480428758-2481-1-git-send-email-yao.qi@linaro.org> <1480591000-19457-1-git-send-email-yao.qi@linaro.org> <1480591000-19457-2-git-send-email-yao.qi@linaro.org> <2b5ae431-5bfb-2adf-aafb-fa2cbda12619@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <2b5ae431-5bfb-2adf-aafb-fa2cbda12619@redhat.com> User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes On Thu, Dec 01, 2016 at 01:07:21PM +0000, Pedro Alves wrote: > Hi Yao, > > On 12/01/2016 11:16 AM, Yao Qi wrote: > > > + else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ > > + || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ > > + && (inst.opcode->op == OP_STR_POS > > + || inst.opcode->op == OP_STRF_POS))) > > + && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM > > + && strcmp ("str", inst.opcode->name) == 0) > > + { > > + /* STR (immediate) */ > > + unsigned int rt = inst.operands[0].reg.regno; > > + int32_t imm = inst.operands[1].addr.offset.imm; > > + unsigned rn = inst.operands[1].addr.base_regno; > > Mixed "unsigned int" vs "unsigned" style. > Fixed. > > + int is64 > > "bool". Fixed. > > > + { > > + struct aarch64_prologue_cache cache; > > + cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); > > + > > + const uint32_t insns[] = { > > "static const". Sorry, my fault. > Fixed. > Othewrise, code-style-wise LGTM. Thanks much for updating. > Patch below is pushed in. diff --git a/gdb/ChangeLog b/gdb/ChangeLog index b4dd117..72eeea4 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,6 +1,13 @@ 2016-12-02 Yao Qi Pedro Alves + * aarch64-tdep.c (aarch64_analyze_prologue): Recognize STR + instruction. + (aarch64_analyze_prologue_test): More tests. + +2016-12-02 Yao Qi + Pedro Alves + * aarch64-tdep.c: Include "selftest.h". (abstract_instruction_reader): New class. (instruction_reader): New class. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 576ee70..590dcf6 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -395,6 +395,35 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, regs[rn] = pv_add_constant (regs[rn], imm); } + else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ + || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ + && (inst.opcode->op == OP_STR_POS + || inst.opcode->op == OP_STRF_POS))) + && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM + && strcmp ("str", inst.opcode->name) == 0) + { + /* STR (immediate) */ + unsigned int rt = inst.operands[0].reg.regno; + int32_t imm = inst.operands[1].addr.offset.imm; + unsigned int rn = inst.operands[1].addr.base_regno; + bool is64 + = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); + gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt + || inst.operands[0].type == AARCH64_OPND_Ft); + + if (inst.operands[0].type == AARCH64_OPND_Ft) + { + /* Only bottom 64-bit of each V register (D register) need + to be preserved. */ + gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); + rt += AARCH64_X_REGISTER_COUNT; + } + + pv_area_store (stack, pv_add_constant (regs[rn], imm), + is64 ? 8 : 4, regs[rt]); + if (inst.operands[1].addr.writeback) + regs[rn] = pv_add_constant (regs[rn], imm); + } else if (inst.opcode->iclass == testbranch) { /* Stop analysis on branch. */ @@ -545,6 +574,52 @@ aarch64_analyze_prologue_test (void) == -1); } } + + /* Test a prologue in which STR is used and frame pointer is not + used. */ + { + struct aarch64_prologue_cache cache; + cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); + + static const uint32_t insns[] = { + 0xf81d0ff3, /* str x19, [sp, #-48]! */ + 0xb9002fe0, /* str w0, [sp, #44] */ + 0xf90013e1, /* str x1, [sp, #32]*/ + 0xfd000fe0, /* str d0, [sp, #24] */ + 0xaa0203f3, /* mov x19, x2 */ + 0xf94013e0, /* ldr x0, [sp, #32] */ + }; + instruction_reader_test reader (insns); + + CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); + + SELF_CHECK (end == 4 * 5); + + SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); + SELF_CHECK (cache.framesize == 48); + + for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) + { + if (i == 1) + SELF_CHECK (cache.saved_regs[i].addr == -16); + else if (i == 19) + SELF_CHECK (cache.saved_regs[i].addr == -48); + else + SELF_CHECK (cache.saved_regs[i].addr == -1); + } + + for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) + { + int regnum = gdbarch_num_regs (gdbarch); + + if (i == 0) + SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr + == -24); + else + SELF_CHECK (cache.saved_regs[i + regnum + AARCH64_D0_REGNUM].addr + == -1); + } + } } } // namespace selftests #endif /* GDB_SELF_TEST */