From patchwork Thu Aug 27 17:41:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulrich Weigand X-Patchwork-Id: 8487 Received: (qmail 83875 invoked by alias); 27 Aug 2015 17:42:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 83853 invoked by uid 89); 27 Aug 2015 17:42:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.9 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 X-HELO: e06smtp14.uk.ibm.com Received: from e06smtp14.uk.ibm.com (HELO e06smtp14.uk.ibm.com) (195.75.94.110) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (CAMELLIA256-SHA encrypted) ESMTPS; Thu, 27 Aug 2015 17:42:03 +0000 Received: from /spool/local by e06smtp14.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 27 Aug 2015 18:42:00 +0100 Received: from d06dlp01.portsmouth.uk.ibm.com (9.149.20.13) by e06smtp14.uk.ibm.com (192.168.101.144) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; Thu, 27 Aug 2015 18:41:59 +0100 X-MailFrom: uweigand@de.ibm.com X-RcptTo: gdb-patches@sourceware.org Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id CEE3D17D805D for ; Thu, 27 Aug 2015 18:43:38 +0100 (BST) Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id t7RHfueh34865386 for ; Thu, 27 Aug 2015 17:41:59 GMT Received: from d06av09.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id t7RHfl4R020670 for ; Thu, 27 Aug 2015 11:41:47 -0600 Received: from oc7340732750.ibm.com (dyn-9-152-213-24.boeblingen.de.ibm.com [9.152.213.24]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id t7RHfl7i020526 for ; Thu, 27 Aug 2015 11:41:47 -0600 Received: by oc7340732750.ibm.com (Postfix, from userid 500) id E853939FA; Thu, 27 Aug 2015 19:41:37 +0200 (CEST) Subject: [pushed][Cell/B.E.] Make parse_spufs_run more robust To: gdb-patches@sourceware.org Date: Thu, 27 Aug 2015 19:41:37 +0200 (CEST) From: "Ulrich Weigand" MIME-Version: 1.0 Message-Id: <20150827174137.E853939FA@oc7340732750.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15082717-0017-0000-0000-0000053B958B Hello, with recent changes to inferior handling, parse_spufs_run needs to be more careful in assumptions it makes. In particular, this patch: - Bails out early if the current inferior has not yet been registered (e.g. during fork procession) to avoid assertion failures in register cache code. - Sets inferior_ptid to the current ptid while calling target_read_memory to make sure the correct process is accessed if parse_spufs_run is called early when inferior_ptid has not yet been switched by the caller. Tested on Cell/B.E., pushed to mainline. Bye, Ulrich ChangeLog: * spu-multiarch.c (parse_spufs_run): Bail out if inferior is not registered yet. Set inferior_ptid while calling target_read_memory. Index: binutils-gdb/gdb/spu-multiarch.c =================================================================== --- binutils-gdb.orig/gdb/spu-multiarch.c +++ binutils-gdb/gdb/spu-multiarch.c @@ -56,6 +56,7 @@ static int parse_spufs_run (ptid_t ptid, int *fd, CORE_ADDR *addr) { enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); + struct cleanup *old_chain; struct gdbarch_tdep *tdep; struct regcache *regcache; gdb_byte buf[4]; @@ -65,12 +66,21 @@ parse_spufs_run (ptid_t ptid, int *fd, C if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_powerpc) return 0; + /* If we're called too early (e.g. after fork), we cannot + access the inferior yet. */ + if (find_inferior_ptid (ptid) == NULL) + return 0; + /* Get PPU-side registers. */ regcache = get_thread_arch_regcache (ptid, target_gdbarch ()); tdep = gdbarch_tdep (target_gdbarch ()); /* Fetch instruction preceding current NIP. */ - if (target_read_memory (regcache_read_pc (regcache) - 4, buf, 4) != 0) + old_chain = save_inferior_ptid (); + inferior_ptid = ptid; + regval = target_read_memory (regcache_read_pc (regcache) - 4, buf, 4); + do_cleanups (old_chain); + if (regval != 0) return 0; /* It should be a "sc" instruction. */ if (extract_unsigned_integer (buf, 4, byte_order) != INSTR_SC)