From patchwork Wed Feb 5 09:47:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nelson Chu X-Patchwork-Id: 37685 Received: (qmail 60556 invoked by alias); 5 Feb 2020 09:47:38 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 60457 invoked by uid 89); 5 Feb 2020 09:47:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-pf1-f196.google.com Received: from mail-pf1-f196.google.com (HELO mail-pf1-f196.google.com) (209.85.210.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Feb 2020 09:47:35 +0000 Received: by mail-pf1-f196.google.com with SMTP id n7so943538pfn.0 for ; Wed, 05 Feb 2020 01:47:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=AvzyeO5JbYcfIvJK6Mh9vnuGfPiDKd/R8LIV4bjHkpc=; b=W+/khU5u9vA7sboXBMq6JlifDbHYvGfTUxwrZl4mkj94eFlhm6U3xXgJ0TERbNxhRY Uxo7OR0+aFK7BFDaiBNfBY/YqTR4vjzXl21zaE8WJZdq71/Hm66xrDUMjLHCQNA/OXkE ALrk8KYmGDL5Wero86AhMSfwGpl5WByedZdln/qQfnpbDsOjDSLPXVtGU4CEdY9i2V9N s5QlUThY8UgFG72m1hkG0nuhFBteed2OEQt3JG5vJlqTqsGG5dn03bgNahCPzfR7K4V1 M+k2yjJ1L2tpmbt4f5TbB/5PdBTQ6HG/lWpnqIRJbpcQ+5rtVMLnGgv4WxdcXDgvtFpV ePSQ== Return-Path: Received: from gamma05.internal.sifive.com ([64.62.193.194]) by smtp.gmail.com with ESMTPSA id a22sm29847466pfk.108.2020.02.05.01.47.33 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 05 Feb 2020 01:47:33 -0800 (PST) From: Nelson Chu To: gdb-patches@sourceware.org Subject: [PATCH v4 2/3] RISC-V: Disable the CSR checking by default. Date: Wed, 5 Feb 2020 01:47:24 -0800 Message-Id: <1580896045-3725-3-git-send-email-nelson.chu@sifive.com> In-Reply-To: <1580896045-3725-1-git-send-email-nelson.chu@sifive.com> References: <1580896045-3725-1-git-send-email-nelson.chu@sifive.com> X-IsSubscribed: yes Add new .option `csr-check/no-csr-check` and GAS option `-mcsr-check /-mno-csr-check` to enbale/disable the CSR checking. Disable the CSR checking by default. gas/ * config/tc-riscv.c: Add new .option and GAS options to enbale/disable the CSR checking. We disable the CSR checking by default. (reg_lookup_internal): Check the `riscv_opts.csr_check` before we doing the CSR checking. * doc/c-riscv.texi: Add description for the new .option and assembler options. * testsuite/gas/riscv/priv-reg-fail-fext.d: Add `-mcsr-check` to enable the CSR checking. * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: Likewise. --- gas/config/tc-riscv.c | 22 +++++++++++++++++++++- gas/doc/c-riscv.texi | 13 +++++++++++++ gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 2 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 2 +- 4 files changed, 36 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 75b58c2..f95c775 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -83,6 +83,7 @@ struct riscv_set_options int rve; /* Generate RVE code. */ int relax; /* Emit relocs the linker is allowed to relax. */ int arch_attr; /* Emit arch attribute. */ + int csr_check; /* Enable the CSR checking. */ }; static struct riscv_set_options riscv_opts = @@ -92,6 +93,7 @@ static struct riscv_set_options riscv_opts = 0, /* rve */ 1, /* relax */ DEFAULT_RISCV_ATTR, /* arch_attr */ + 0. /* csr_check */ }; static void @@ -572,7 +574,9 @@ reg_lookup_internal (const char *s, enum reg_class class) if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) return -1; - if (class == RCLASS_CSR && !reg_csr_lookup_internal (s)) + if (class == RCLASS_CSR + && riscv_opts.csr_check + && !reg_csr_lookup_internal (s)) return -1; return DECODE_REG_NUM (r); @@ -2272,6 +2276,8 @@ enum options OPTION_NO_RELAX, OPTION_ARCH_ATTR, OPTION_NO_ARCH_ATTR, + OPTION_CSR_CHECK, + OPTION_NO_CSR_CHECK, OPTION_END_OF_ENUM }; @@ -2286,6 +2292,8 @@ struct option md_longopts[] = {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, + {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK}, + {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK}, {NULL, no_argument, NULL, 0} }; @@ -2364,6 +2372,14 @@ md_parse_option (int c, const char *arg) riscv_opts.arch_attr = FALSE; break; + case OPTION_CSR_CHECK: + riscv_opts.csr_check = TRUE; + break; + + case OPTION_NO_CSR_CHECK: + riscv_opts.csr_check = FALSE; + break; + default: return 0; } @@ -2756,6 +2772,10 @@ s_riscv_option (int x ATTRIBUTE_UNUSED) riscv_opts.relax = TRUE; else if (strcmp (name, "norelax") == 0) riscv_opts.relax = FALSE; + else if (strcmp (name, "csr-check") == 0) + riscv_opts.csr_check = TRUE; + else if (strcmp (name, "no-csr-check") == 0) + riscv_opts.csr_check = FALSE; else if (strcmp (name, "push") == 0) { struct riscv_option_stack *s; diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index 0976651..83187dc 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -59,6 +59,15 @@ required to materialize symbol addresses. (default) @item -mno-relax Don't do linker relaxations. +@cindex @samp{-mcsr-check} option, RISC-V +@item -mcsr-check +Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. +The ISA-dependent CSR are only valid when the specific ISA is set. The +read-only CSR can not be written by the CSR instructions. + +@cindex @samp{-mno-csr-check} option, RISC-V +@item -mno-csr-check +Don't do CSR cheching. @end table @c man end @@ -160,6 +169,10 @@ opportunistically relax some code sequences, but sometimes this behavior is not desirable. @end table +@item csr-check +@itemx no-csr-check +Enables or disables the CSR checking. + @cindex INSN directives @item .insn @var{value} @itemx .insn @var{value} diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d index 78ab758..da53566 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d @@ -1,3 +1,3 @@ -#as: -march=rv32i +#as: -march=rv32i -mcsr-check #source: priv-reg.s #warning_output: priv-reg-fail-fext.l diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d index 5dc840a..d71b261 100644 --- a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d @@ -1,3 +1,3 @@ -#as: -march=rv64if +#as: -march=rv64if -mcsr-check #source: priv-reg.s #warning_output: priv-reg-fail-rv32-only.l