From patchwork Mon Jun 18 15:31:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 27907 Received: (qmail 94318 invoked by alias); 18 Jun 2018 15:31:47 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 94193 invoked by uid 89); 18 Jun 2018 15:31:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_PASS autolearn=unavailable version=3.3.2 spammy= X-HELO: sesbmg23.ericsson.net Received: from sesbmg23.ericsson.net (HELO sesbmg23.ericsson.net) (193.180.251.37) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Jun 2018 15:31:44 +0000 Received: from ESESBMB501.ericsson.se (Unknown_Domain [153.88.183.114]) by sesbmg23.ericsson.net (Symantec Mail Security) with SMTP id 24.12.31551.A50D72B5; Mon, 18 Jun 2018 17:31:38 +0200 (CEST) Received: from ESESBMB501.ericsson.se (153.88.183.168) by ESESBMB501.ericsson.se (153.88.183.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Mon, 18 Jun 2018 17:31:38 +0200 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (153.88.183.157) by ESESBMB501.ericsson.se (153.88.183.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3 via Frontend Transport; Mon, 18 Jun 2018 17:31:38 +0200 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=simon.marchi@ericsson.com; Received: from elxacz23q12.ca.am.ericsson.se (192.75.88.130) by BYAPR15MB2390.namprd15.prod.outlook.com (2603:10b6:a02:8c::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.863.19; Mon, 18 Jun 2018 15:31:34 +0000 From: Simon Marchi To: , CC: Nick Clifton , Alan Modra , Joseph Myers , Simon Marchi Subject: [PATCH] include: Sync with GCC Date: Mon, 18 Jun 2018 11:31:15 -0400 Message-Id: <1529335875-26732-1-git-send-email-simon.marchi@ericsson.com> MIME-Version: 1.0 X-ClientProxiedBy: SN4PR0501CA0040.namprd05.prod.outlook.com (2603:10b6:803:41::17) To BYAPR15MB2390.namprd15.prod.outlook.com (2603:10b6:a02:8c::30) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d5fb7d88-e69c-41c3-2b20-08d5d53093fa X-MS-TrafficTypeDiagnostic: BYAPR15MB2390: X-Exchange-Antispam-Report-Test: UriScan:(22074186197030)(138986009662008)(85827821059158)(183786458502308); X-MS-Exchange-SenderADCheck: 1 X-Forefront-PRVS: 0707248B64 Received-SPF: None (protection.outlook.com: ericsson.com does not designate permitted sender hosts) SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Jun 2018 15:31:34.9804 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5fb7d88-e69c-41c3-2b20-08d5d53093fa X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 92e84ceb-fbfd-47ab-be52-080c6b87953f X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR15MB2390 X-OriginatorOrg: ericsson.com X-IsSubscribed: yes Bring changes from GCC in shared headers. include/ChangeLog: Sync with GCC 2018-05-24 Tom Rix * dwarf2.def (DW_FORM_strx*, DW_FORM_addrx*): New. 2017-11-20 Kito Cheng * longlong.h [__riscv] (__umulsidi3): Define. [__riscv] (umul_ppmm): Likewise. [__riscv] (__muluw3): Likewise. --- include/dwarf2.def | 8 ++++++++ include/longlong.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/include/dwarf2.def b/include/dwarf2.def index 3becd7f..358844f 100644 --- a/include/dwarf2.def +++ b/include/dwarf2.def @@ -220,6 +220,14 @@ DW_FORM (DW_FORM_implicit_const, 0x21) DW_FORM (DW_FORM_loclistx, 0x22) DW_FORM (DW_FORM_rnglistx, 0x23) DW_FORM (DW_FORM_ref_sup8, 0x24) +DW_FORM (DW_FORM_strx1, 0x25) +DW_FORM (DW_FORM_strx2, 0x26) +DW_FORM (DW_FORM_strx3, 0x27) +DW_FORM (DW_FORM_strx4, 0x28) +DW_FORM (DW_FORM_addrx1, 0x29) +DW_FORM (DW_FORM_addrx2, 0x2a) +DW_FORM (DW_FORM_addrx3, 0x2b) +DW_FORM (DW_FORM_addrx4, 0x2c) /* Extensions for Fission. See http://gcc.gnu.org/wiki/DebugFission. */ DW_FORM (DW_FORM_GNU_addr_index, 0x1f01) DW_FORM (DW_FORM_GNU_str_index, 0x1f02) diff --git a/include/longlong.h b/include/longlong.h index fb982dd..7f3dc17 100644 --- a/include/longlong.h +++ b/include/longlong.h @@ -1050,6 +1050,56 @@ extern UDItype __umulsidi3 (USItype, USItype); } while (0) #endif +#if defined(__riscv) +#ifdef __riscv_mul +#define __umulsidi3(u,v) ((UDWtype)(UWtype)(u) * (UWtype)(v)) +#define __muluw3(a, b) ((UWtype)(a) * (UWtype)(b)) +#else +#if __riscv_xlen == 32 + #define MULUW3 "call __mulsi3" +#elif __riscv_xlen == 64 + #define MULUW3 "call __muldi3" +#else +#error unsupport xlen +#endif /* __riscv_xlen */ +/* We rely on the fact that MULUW3 doesn't clobber the t-registers. + It can get better register allocation result. */ +#define __muluw3(a, b) \ + ({ \ + register UWtype __op0 asm ("a0") = a; \ + register UWtype __op1 asm ("a1") = b; \ + asm volatile (MULUW3 \ + : "+r" (__op0), "+r" (__op1) \ + : \ + : "ra", "a2", "a3"); \ + __op0; \ + }) +#endif /* __riscv_mul */ +#define umul_ppmm(w1, w0, u, v) \ + do { \ + UWtype __x0, __x1, __x2, __x3; \ + UHWtype __ul, __vl, __uh, __vh; \ + \ + __ul = __ll_lowpart (u); \ + __uh = __ll_highpart (u); \ + __vl = __ll_lowpart (v); \ + __vh = __ll_highpart (v); \ + \ + __x0 = __muluw3 (__ul, __vl); \ + __x1 = __muluw3 (__ul, __vh); \ + __x2 = __muluw3 (__uh, __vl); \ + __x3 = __muluw3 (__uh, __vh); \ + \ + __x1 += __ll_highpart (__x0);/* this can't give carry */ \ + __x1 += __x2; /* but this indeed can */ \ + if (__x1 < __x2) /* did we get it? */ \ + __x3 += __ll_B; /* yes, add it in the proper pos. */ \ + \ + (w1) = __x3 + __ll_highpart (__x1); \ + (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \ + } while (0) +#endif /* __riscv */ + #if defined(__sh__) && W_TYPE_SIZE == 32 #ifndef __sh1__ #define umul_ppmm(w1, w0, u, v) \