From patchwork Fri Nov 25 19:46:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ambrogino Modigliani X-Patchwork-Id: 17929 Received: (qmail 35226 invoked by alias); 25 Nov 2016 19:47:49 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 33613 invoked by uid 89); 25 Nov 2016 19:47:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=9907, ISA, collaborative, 9547 X-HELO: mail-wm0-f66.google.com Received: from mail-wm0-f66.google.com (HELO mail-wm0-f66.google.com) (74.125.82.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Nov 2016 19:47:18 +0000 Received: by mail-wm0-f66.google.com with SMTP id a20so9187566wme.2 for ; Fri, 25 Nov 2016 11:47:18 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=g6eu4vujVwJ0JD+8WwZamsgwokUMPjtfez1L2a8s0JA=; b=ZBQBesP3EJwn/JGt9gM4Vcx9teetl3robAVHH9q52G7IqUlFd8u3yWwCp6vSBmsnKs yv84Awg1yr1+/3BDu6Wd4Q1vLkRkw3xAXZCcG6LIe14bn0E/ejSSnWUnQ8l3iHKJRWDe /AMb0zqZDfhIme+NE+xPuG4U6NDKZ9vcPwS+dMWW07buJdGaCb+6EUkxIIEF7ia+acgn K+cEaB+N9HXW4p9p7Y85+nqZdNWfivX+rSxKiiOrlWSurbt0xDpAhYj6bfuEdlGl2sM8 /I7PGMk2jtB2jx7LFXoLVrLx8d2j6QUhhxc0YChXcLb7MLPs/05vmyuIGa0jeC9cwUNE UE1Q== X-Gm-Message-State: AKaTC02XgRzhWcQZKBJKBjvlGhoRTyDmwynmv1SRCrPFQbGig+fFGChVn7uEKtfueoJD5g== X-Received: by 10.28.182.70 with SMTP id g67mr9786789wmf.90.1480103236422; Fri, 25 Nov 2016 11:47:16 -0800 (PST) Received: from localhost.localdomain ([95.180.71.38]) by smtp.googlemail.com with ESMTPSA id l67sm14208774wmf.0.2016.11.25.11.47.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 25 Nov 2016 11:47:15 -0800 (PST) From: Ambrogino Modigliani X-Google-Original-From: Ambrogino Modigliani To: gdb-patches@sourceware.org, pedro_alves@portugalmail.pt, ambrogino.modigliani@gmail.com, ambrogino.modigliani@mail.com Subject: [PATCH 10/17] Fix spelling in comments in .cpu files (cpu) Date: Fri, 25 Nov 2016 20:46:36 +0100 Message-Id: <1480103203-9710-11-git-send-email-ambrogino.modigliani@mail.com> In-Reply-To: <1480103203-9710-1-git-send-email-ambrogino.modigliani@mail.com> References: <1480103203-9710-1-git-send-email-ambrogino.modigliani@mail.com> cpu/ChangeLog: * m32c.cpu: Fix spelling in comments. * m32r.cpu: Fix spelling in comments. * mt.cpu: Fix spelling in comments. * or1k.cpu: Fix spelling in comments. * xstormy16.cpu: Fix spelling in comments. --- cpu/m32c.cpu | 2 +- cpu/m32r.cpu | 2 +- cpu/mt.cpu | 2 +- cpu/or1k.cpu | 2 +- cpu/xstormy16.cpu | 8 ++++---- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index bcc3616..7d313bc 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -10292,7 +10292,7 @@ (binary-arith32-imm-dst-defn HI HI .w 1 stz X #x9 #x0 #xF stz-sem) ;------------------------------------------------------------- -; stzx - store on zero extention +; stzx - store on zero extension ;------------------------------------------------------------- (define-pmacro (stzx-sem mode src1 src2 dst) diff --git a/cpu/m32r.cpu b/cpu/m32r.cpu index 003c848..8de8a43 100644 --- a/cpu/m32r.cpu +++ b/cpu/m32r.cpu @@ -742,7 +742,7 @@ (dnop disp16 "16 bit displacement" () h-iaddr f-disp16) (dnop disp24 "24 bit displacement" (RELAX) h-iaddr f-disp24) -; These hardware elements are refered to frequently. +; These hardware elements are referred to frequently. (dnop condbit "condition bit" (SEM-ONLY) h-cond f-nil) (dnop accum "accumulator" (SEM-ONLY) h-accum f-nil) diff --git a/cpu/mt.cpu b/cpu/mt.cpu index bb987f3..bf49a28 100644 --- a/cpu/mt.cpu +++ b/cpu/mt.cpu @@ -163,7 +163,7 @@ ; f-imm16: 16 bit immediate value when not an offset. ; f-imm16a: 16 bit immediate value when it's a pc-rel offset. ; f-uu4a: unused 4 bit field. -; f-uu4b: second unsed 4 bit field. +; f-uu4b: second unused 4 bit field. ; f-uu1: unused 1 bit field ; f-uu12: unused 12 bit field. ; f-uu16: unused 16 bit field. diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu index 3a932bc..169344c 100644 --- a/cpu/or1k.cpu +++ b/cpu/or1k.cpu @@ -20,7 +20,7 @@ (include "simplify.inc") ; The OpenRISC family is a set of RISC microprocessor architectures with an -; emphasis on scalability and is targetted at embedded use. +; emphasis on scalability and is targeted at embedded use. ; The CPU RTL development is a collaborative open source effort. ; http://opencores.org/or1k ; http://openrisc.net diff --git a/cpu/xstormy16.cpu b/cpu/xstormy16.cpu index ae7e042..61b27cb 100644 --- a/cpu/xstormy16.cpu +++ b/cpu/xstormy16.cpu @@ -941,7 +941,7 @@ (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)) (set Rs (add Rs (add ws2 1))) ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. + ; addition *is* propagated into the base register. (if (eq Rs 0) (set Rb (add Rb 1))) ) () @@ -954,7 +954,7 @@ (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) (sequence () ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. + ; subtraction *is* propagated into the base register. (if (eq Rs 0) (set Rb (sub Rb 1))) (set Rs (sub Rs (add ws2 1))) (if ws2 @@ -990,7 +990,7 @@ (set-psw-nowrite (index-of Rdm) Rdm ws2) (set Rs (add Rs (add ws2 1))) ; Note - despite the XStormy16 ISA documentation the - ; addition *is* propogated into the base register. + ; addition *is* propagated into the base register. (if (eq Rs 0) (set Rb (add Rb 1))) ) () @@ -1003,7 +1003,7 @@ (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12) (sequence () ; Note - despite the XStormy16 ISA documentation the - ; subtraction *is* propogated into the base register. + ; subtraction *is* propagated into the base register. (if (eq Rs 0) (set Rb (sub Rb 1))) (set Rs (sub Rs (add ws2 1))) (set-psw-nowrite (index-of Rdm) Rdm ws2)