From patchwork Fri Nov 25 19:46:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ambrogino Modigliani X-Patchwork-Id: 17913 Received: (qmail 27804 invoked by alias); 25 Nov 2016 19:46:32 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 27793 invoked by uid 89); 25 Nov 2016 19:46:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=H*Ad:D*mail.com, stall, STATE, occurred X-HELO: mail-wm0-f66.google.com Received: from mail-wm0-f66.google.com (HELO mail-wm0-f66.google.com) (74.125.82.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Nov 2016 19:46:30 +0000 Received: by mail-wm0-f66.google.com with SMTP id u144so9151778wmu.0 for ; Fri, 25 Nov 2016 11:46:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=V53dRypMov7FaXes6UDX926PaLkA/V8K9y5rXlatApo=; b=YGYRHI7w+eaKOirXbAMOIKWPEv//8eYE4FWmQ8DttyBvqATj0eMCVeQkJTSTJ2Y/hc warkhDzH5HS0Zyw2Nnl8n/iy0F+BflgdVHATKr40H4vVBEa8ZSFrd8LPTVJPK30t9E4V 5Lf1CtbpP1QkY1lqKkIjgadvvqABboSPN/EDzvHYAcd+rtooxv1vrB31X+nqdUtnfmJB Ytbl0fNOhAYAw5DdlkG20YghYz5HRWs1jjSCTOEbOxr3qLUSaA3at6gLwnGLjNlMFYqz KveSFNQzoJ0Mb7sDEwD6crYlqKGrg2buyJZAOfe6vYz2awhmKsRz5owaS9nguSza1O86 0hGA== X-Gm-Message-State: AKaTC00PG/Njm3CtCidbwpVZNfJdx5mr5F4riiNfbsaY6YY7liMzRww87EwR9xa/Wj2jNg== X-Received: by 10.28.26.197 with SMTP id a188mr8852108wma.93.1480103188655; Fri, 25 Nov 2016 11:46:28 -0800 (PST) Received: from localhost.localdomain ([95.180.71.38]) by smtp.googlemail.com with ESMTPSA id g197sm14980227wmd.15.2016.11.25.11.46.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 25 Nov 2016 11:46:28 -0800 (PST) From: Ambrogino Modigliani X-Google-Original-From: Ambrogino Modigliani To: gdb-patches@sourceware.org, pedro_alves@portugalmail.pt, ambrogino.modigliani@gmail.com, ambrogino.modigliani@mail.com Subject: [PATCH 3/5] Fix spelling in comments in .igen files (sim) Date: Fri, 25 Nov 2016 20:46:08 +0100 Message-Id: <1480103170-9627-4-git-send-email-ambrogino.modigliani@mail.com> In-Reply-To: <1480103170-9627-1-git-send-email-ambrogino.modigliani@mail.com> References: <1480103170-9627-1-git-send-email-ambrogino.modigliani@mail.com> sim/mips/ChangeLog: * m16.igen: Fix spelling in comments. * mips.igen: Fix spelling in comments. sim/v850/ChangeLog: * v850.igen: Fix spelling in comments. --- sim/mips/m16.igen | 4 ++-- sim/mips/mips.igen | 6 +++--- sim/v850/v850.igen | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen index 74adacd..db58184 100644 --- a/sim/mips/m16.igen +++ b/sim/mips/m16.igen @@ -1044,12 +1044,12 @@ return target; } -// compute basepc dependant on us being in a delay slot +// compute basepc dependent on us being in a delay slot :function:::address_word:basepc: { if (STATE & simDELAYSLOT) { - return DSPC; /* return saved address of preceeding jmp */ + return DSPC; /* return saved address of preceding jmp */ } else { diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 522cad6..99caefb 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -254,9 +254,9 @@ // suggest they don't. // // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have -// these restrictions, while others, like the VR5500, don't. To accomodate +// these restrictions, while others, like the VR5500, don't. To accommodate // such differences, the MIPS IV and MIPS V version of these helper functions -// use auxillary routines to determine whether the restriction applies. +// use auxiliary routines to determine whether the restriction applies. // check_mf_cycles: // @@ -417,7 +417,7 @@ *micromips32: *micromips64: { - /* FIXME: could record the fact that a stall occured if we want */ + /* FIXME: could record the fact that a stall occurred if we want */ signed64 time = sim_events_time (SD); hi->op.timestamp = time; lo->op.timestamp = time; diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 41a9075..af9b57b 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -1149,7 +1149,7 @@ rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry); @@ -1214,7 +1214,7 @@ rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry);