From patchwork Sun Nov 20 15:06:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ambrogino Modigliani X-Patchwork-Id: 17605 Received: (qmail 76313 invoked by alias); 20 Nov 2016 15:07:04 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 75944 invoked by uid 89); 20 Nov 2016 15:07:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.4 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=no version=3.3.2 spammy=STATE, H*Ad:D*pt, Hx-languages-length:2732 X-HELO: mail-wm0-f66.google.com Received: from mail-wm0-f66.google.com (HELO mail-wm0-f66.google.com) (74.125.82.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 20 Nov 2016 15:07:00 +0000 Received: by mail-wm0-f66.google.com with SMTP id m203so19729905wma.3 for ; Sun, 20 Nov 2016 07:06:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=Z1fsYKH1/RFEKSN5JamL32X0cVBjnf04m3wcF75T/QE=; b=LOCw/bkOtGEQkypA4V1zvsaL7FldIx/JTLrlB3WnfUM03WJhBybo8FWAViy02prXAp s2p3emqkh0J05BW3t480wkY6TNDMqxFMEIzfzhk31usq26slsL9nJTLC2kMtDdXFgk4y vErYUnrF375pKHGCydxD3865iX6ONDNcOLezYxfyBSxEo/Fxt2R1B3JhZCHtqne3rUZf qEDvqrDvkLUSAit8C4mM9c+SP4SOXZx8RURE2C0fT4YTuB+UCMnuaPcnNP5sagI2vSOB ba4JAdLsio1fTiw8dMShJzX6qnV4sRxEioIy02/taVXXIYVPEQNxCasKE5mjUp6cn/bm zT4Q== X-Gm-Message-State: AKaTC01A0EeEIryTxqXpzLAcp+kBbduqQ2ylyH8pYl+m2DTF5zK5IESD8/+ieY8tZQ5vVQ== X-Received: by 10.28.94.76 with SMTP id s73mr9425168wmb.107.1479654417963; Sun, 20 Nov 2016 07:06:57 -0800 (PST) Received: from localhost.localdomain ([95.180.71.38]) by smtp.googlemail.com with ESMTPSA id v2sm19793444wja.41.2016.11.20.07.06.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 20 Nov 2016 07:06:57 -0800 (PST) From: Ambrogino Modigliani X-Google-Original-From: Ambrogino Modigliani To: gdb-patches@sourceware.org, pedro_alves@portugalmail.pt Subject: [PATCH 12/20] Fix spelling mistakes in comments in .igen files Date: Sun, 20 Nov 2016 16:06:13 +0100 Message-Id: <1479654381-20698-13-git-send-email-ambrogino.modigliani@mail.com> In-Reply-To: <1479654381-20698-1-git-send-email-ambrogino.modigliani@mail.com> References: <1479654381-20698-1-git-send-email-ambrogino.modigliani@mail.com> sim/mips/ChangeLog: * sim/mips/m16.igen: Fix spelling in comments. * sim/mips/mips.igen: Fix spelling in comments. sim/v850/ChangeLog: * sim/v850/v850.igen: Fix spelling in comments. --- sim/mips/m16.igen | 4 ++-- sim/mips/mips.igen | 6 +++--- sim/v850/v850.igen | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/sim/mips/m16.igen b/sim/mips/m16.igen index 74adacd..db58184 100644 --- a/sim/mips/m16.igen +++ b/sim/mips/m16.igen @@ -1044,12 +1044,12 @@ return target; } -// compute basepc dependant on us being in a delay slot +// compute basepc dependent on us being in a delay slot :function:::address_word:basepc: { if (STATE & simDELAYSLOT) { - return DSPC; /* return saved address of preceeding jmp */ + return DSPC; /* return saved address of preceding jmp */ } else { diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen index 522cad6..99caefb 100644 --- a/sim/mips/mips.igen +++ b/sim/mips/mips.igen @@ -254,9 +254,9 @@ // suggest they don't. // // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have -// these restrictions, while others, like the VR5500, don't. To accomodate +// these restrictions, while others, like the VR5500, don't. To accommodate // such differences, the MIPS IV and MIPS V version of these helper functions -// use auxillary routines to determine whether the restriction applies. +// use auxiliary routines to determine whether the restriction applies. // check_mf_cycles: // @@ -417,7 +417,7 @@ *micromips32: *micromips64: { - /* FIXME: could record the fact that a stall occured if we want */ + /* FIXME: could record the fact that a stall occurred if we want */ signed64 time = sim_events_time (SD); hi->op.timestamp = time; lo->op.timestamp = time; diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 41a9075..af9b57b 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -1149,7 +1149,7 @@ rrrrr,111111,RRRRR + wwww,0011110,mmmm,0:XI:::mac hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry); @@ -1214,7 +1214,7 @@ rrrrr,111111,RRRRR + wwww,0011111,mmmm,0:XI:::macu hi = (((op0 >> 16) & 0xFFFF) * ((op1 >> 16) & 0xFFFF)); /* We now need to add all of these results together, taking care - to propogate the carries from the additions: */ + to propagate the carries from the additions: */ RdLo = Add32 (lo, (mid1 << 16), & carry); RdHi = carry; RdLo = Add32 (RdLo, (mid2 << 16), & carry);