From patchwork Wed Sep 21 11:28:34 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 15837 Received: (qmail 47729 invoked by alias); 21 Sep 2016 11:29:00 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 47720 invoked by uid 89); 21 Sep 2016 11:28:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=Supply, 6715, reserved X-HELO: mail-wm0-f68.google.com Received: from mail-wm0-f68.google.com (HELO mail-wm0-f68.google.com) (74.125.82.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 21 Sep 2016 11:28:49 +0000 Received: by mail-wm0-f68.google.com with SMTP id w84so8043388wmg.0 for ; Wed, 21 Sep 2016 04:28:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id; bh=mRjhBkgSAwhMsRBjtvVtAjmSFlKa7T8oiBOABtKvdbQ=; b=mOj1tXtfnti6KxWBMfeh2wvOtvq0G3/8REa6vJfFPCUEk13k6zpg+CQKvXZ4A7e+hq eG9Zmw+c2TeDPnFek1vk9EGGioxc2hfkLkO6dwMA6UVXEkwjCws1A73MnCPXU5uY+tty QkluHrEOX19mcKA8kOfRvkVSihS8Q0RVrDdAoFgTLIsFTRsWdLWuIuLw8nOIDgiI/Nb+ h6kuctMRgbmracy0xf0nnK16Ex7AsTLXzF0P3JibNqCQ2zjKBzvNyni+5TmE7KxsdMyh g+VzxmYiNuBEYTbTZARkQNtnZ+tM5npnFVMcHBjyOeLoiMBdAjey8dEeDVNzBPzsqz/4 f2ow== X-Gm-Message-State: AE9vXwOX36SAPqOLH85DIfpXOKVnynonubhG8lN9IKhW+NcGaZ7Me/iz8BUpoyWuCnt6ag== X-Received: by 10.28.45.214 with SMTP id t205mr2550542wmt.107.1474457326901; Wed, 21 Sep 2016 04:28:46 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com ([86.65.39.12]) by smtp.gmail.com with ESMTPSA id r194sm32177667wmf.22.2016.09.21.04.28.43 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Sep 2016 04:28:44 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH master/7.12] Keep reserved bits in CPSR on write Date: Wed, 21 Sep 2016 12:28:34 +0100 Message-Id: <1474457314-32275-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html I cleared reserved bits when reading CPSR. It makes a problem that these bits (zero) are written back to kernel through ptrace, and it changes the state of the processor on some recent kernel, which is unexpected. In this patch, I keep these reserved bits when write CPSR back to hardware. gdb: 2016-09-21 Yao Qi * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep bits 20 to 23. gdb/gdbserver: 2016-09-21 Yao Qi * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to 23. --- gdb/ChangeLog | 5 +++++ gdb/aarch32-linux-nat.c | 11 +++++++++-- gdb/gdbserver/ChangeLog | 5 +++++ gdb/gdbserver/linux-aarch32-low.c | 4 ++++ 4 files changed, 23 insertions(+), 2 deletions(-) diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ef18a19..b7b9e54 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2016-09-21 Yao Qi + + * aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep + bits 20 to 23. + 2016-09-20 Tom Tromey * python/py-value.c (convert_value_from_python): Make PyInt_Check diff --git a/gdb/aarch32-linux-nat.c b/gdb/aarch32-linux-nat.c index 72bf644..2df672d 100644 --- a/gdb/aarch32-linux-nat.c +++ b/gdb/aarch32-linux-nat.c @@ -67,8 +67,15 @@ aarch32_gp_regcache_collect (const struct regcache *regcache, uint32_t *regs, if (arm_apcs_32 && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM)) - regcache_raw_collect (regcache, ARM_PS_REGNUM, - ®s[ARM_CPSR_GREGNUM]); + { + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; + + regcache_raw_collect (regcache, ARM_PS_REGNUM, + ®s[ARM_CPSR_GREGNUM]); + /* Keep reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff) + | (cpsr & 0x00f00000)); + } } /* Supply VFP registers contents, stored in REGS, to REGCACHE. diff --git a/gdb/gdbserver/ChangeLog b/gdb/gdbserver/ChangeLog index c97c777..c1f1dff 100644 --- a/gdb/gdbserver/ChangeLog +++ b/gdb/gdbserver/ChangeLog @@ -1,3 +1,8 @@ +2016-09-21 Yao Qi + + * linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to + 23. + 2016-09-19 Sergio Durigan Junior * server.c (start_inferior): Call target_mourn_inferior instead of diff --git a/gdb/gdbserver/linux-aarch32-low.c b/gdb/gdbserver/linux-aarch32-low.c index e6971d5..463bce6 100644 --- a/gdb/gdbserver/linux-aarch32-low.c +++ b/gdb/gdbserver/linux-aarch32-low.c @@ -62,11 +62,15 @@ arm_fill_gregset (struct regcache *regcache, void *buf) { int i; uint32_t *regs = (uint32_t *) buf; + uint32_t cpsr = regs[ARM_CPSR_GREGNUM]; for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++) collect_register (regcache, i, ®s[i]); collect_register (regcache, ARM_PS_REGNUM, ®s[ARM_CPSR_GREGNUM]); + /* Keep reserved bits bit 20 to bit 23. */ + regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff) + | (cpsr & 0x00f00000)); } /* Supply GP registers contents, stored in BUF, to REGCACHE. */