From patchwork Fri Aug 19 13:34:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 14777 Received: (qmail 119432 invoked by alias); 19 Aug 2016 13:34:55 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 119413 invoked by uid 89); 19 Aug 2016 13:34:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=x30, x29, STP, H*MI:4975 X-HELO: mail-pf0-f196.google.com Received: from mail-pf0-f196.google.com (HELO mail-pf0-f196.google.com) (209.85.192.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 19 Aug 2016 13:34:43 +0000 Received: by mail-pf0-f196.google.com with SMTP id y134so1504529pfg.3 for ; Fri, 19 Aug 2016 06:34:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:subject:date:message-id; bh=iWhyLHk2b1leg5U2rZc9tK0n412xUiYgo/RNejojk/Q=; b=eD5BiXSfGR3iZ8scZGpH7tzCpi77KwLZA8AxEZFRg6hkaqpfNtAKM8QTBNz5fynoyI ZmV0Ty/tF8a8TimaQ2xkUgjPqsBVoMw5u5JGcmra/+7yxv1yAEvhFM5Ra8eGurbBq3Gl Lmfm9k2i+N3mDlSkiMz1zYQ6NQ+xJ39XZ1j4LOVGltm0E10Vc0DPJgdwhcr564hgcpW+ 2hNjGt1RgaAUmzQpChc8pkwf2IJIoJZbcy6r1mcrS66kuzssJATNM3hJONaTnTUrqOls lVEIpXodXBvQpoRgnblxDY82LGFisXMBGIuvVLNQS10Ib/1YnA4It4al4lirOyxz03rX CbSw== X-Gm-Message-State: AEkoouurdOmLKHbilqYw7UvjXg4ZqHWG9+DHo14CT2Da0sjbvd1vR22/dhzNXUK519gLdA== X-Received: by 10.98.80.220 with SMTP id g89mr14195774pfj.12.1471613681956; Fri, 19 Aug 2016 06:34:41 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com (gcc115.osuosl.org. [140.211.9.73]) by smtp.gmail.com with ESMTPSA id p75sm6815346pfa.71.2016.08.19.06.34.40 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Aug 2016 06:34:41 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue Date: Fri, 19 Aug 2016 14:34:36 +0100 Message-Id: <1471613676-4975-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes Nowadays, we only match pre-indexed STP in prologue. Due to the change in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it may generate "STP with base register" in prologue, which GDB doesn't handle. That is to say, previously GCC generates prologue like this, sub sp, sp, #490 stp x29, x30, [sp, #-96]! mov x29, sp with the gcc patch above, GCC generates prologue like like this, sub sp, sp, #4f0 stp x29, x30, [sp] mov x29, sp This patch is to teach GDB to recognize this instruction in prologue analysis. It fixes some fails in gdb.base/break-interp.exp. Regression tested on aarch64-linux with GCC mainline and 4.9.3. I'll push it in. gdb: 2016-08-19 Yao Qi * aarch64-tdep.c (aarch64_analyze_prologue): Handle register based STP instruction. --- gdb/aarch64-tdep.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index e97e2f4..3b7e954 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, is64 ? 8 : 4, regs[rt]); } else if ((inst.opcode->iclass == ldstpair_off - || inst.opcode->iclass == ldstpair_indexed) - && inst.operands[2].addr.preind + || (inst.opcode->iclass == ldstpair_indexed + && inst.operands[2].addr.preind)) && strcmp ("stp", inst.opcode->name) == 0) { + /* STP with addressing mode Pre-indexed and Base register. */ unsigned rt1 = inst.operands[0].reg.regno; unsigned rt2 = inst.operands[1].reg.regno; unsigned rn = inst.operands[2].addr.base_regno;