[master+7.12,AArch64] Match instruction "STP with base register" in prologue

Message ID 1471613676-4975-1-git-send-email-yao.qi@linaro.org
State New, archived
Headers

Commit Message

Yao Qi Aug. 19, 2016, 1:34 p.m. UTC
  Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.  It fixes some fails in gdb.base/break-interp.exp.
Regression tested on aarch64-linux with GCC mainline and 4.9.3.
I'll push it in.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
	based STP instruction.
---
 gdb/aarch64-tdep.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)
  

Comments

Jan Kratochvil Oct. 10, 2016, 8:41 p.m. UTC | #1
On Fri, 19 Aug 2016 15:34:36 +0200, Yao Qi wrote:
> I'll push it in.
[...]
> 2016-08-19  Yao Qi  <yao.qi@linaro.org>
> 
> 	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
> 	based STP instruction.

03bcd7394eefb9399f5ab97919a0463dea274c02 is the first bad commit
commit 03bcd7394eefb9399f5ab97919a0463dea274c02
Author: Yao Qi <yao.qi@linaro.org>
Date:   Fri Aug 19 14:49:31 2016 +0100
    [AArch64] Match instruction "STP with base register" in prologue

FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)
FAIL: gdb.cp/nextoverthrow.exp: continuing to _Unwind_RaiseException (the program exited)
FAIL: gdb.cp/nextoverthrow.exp: finish (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: continuing to Second: resumebpt (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: continuing to done (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: post-check - advance

tbreak _Unwind_RaiseException^M
aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
A problem internal to GDB has been detected,^M
further debugging may prove unreliable.^M
Quit this debugging session? (y or n) FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)

RHEL-7.3-20161007.n.0 Server aarch64
gcc-4.8.5-11.el7.aarch64

Please contact me (possibly also offlist) if you have it unreproducible.


Thanks,
Jan
  
Yao Qi Oct. 11, 2016, 11:25 a.m. UTC | #2
Hi Jan,

On Mon, Oct 10, 2016 at 9:41 PM, Jan Kratochvil
> tbreak _Unwind_RaiseException^M
> aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
> A problem internal to GDB has been detected,^M
> further debugging may prove unreliable.^M
> Quit this debugging session? (y or n) FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)
>
> RHEL-7.3-20161007.n.0 Server aarch64
> gcc-4.8.5-11.el7.aarch64
>
> Please contact me (possibly also offlist) if you have it unreproducible.
>

This internal error is caused by instruction "stp with FP registers" in
the prologue.  The instruction triggers this assert is like
"stp d8, d9, [sp, #imm]".  However, aarch64 gdb doesn't track FP registers
at all in prologue analysis.

Could you open a ticket in bugzilla for this error?  I am testing a patch.
  
Jan Kratochvil Oct. 11, 2016, 12:40 p.m. UTC | #3
On Tue, 11 Oct 2016 13:25:31 +0200, Yao Qi wrote:
> Could you open a ticket in bugzilla for this error?  I am testing a patch.

https://sourceware.org/bugzilla/show_bug.cgi?id=20682


Thanks,
Jan
  

Patch

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e97e2f4..3b7e954 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -322,10 +322,11 @@  aarch64_analyze_prologue (struct gdbarch *gdbarch,
 			 is64 ? 8 : 4, regs[rt]);
 	}
       else if ((inst.opcode->iclass == ldstpair_off
-		|| inst.opcode->iclass == ldstpair_indexed)
-	       && inst.operands[2].addr.preind
+		|| (inst.opcode->iclass == ldstpair_indexed
+		    && inst.operands[2].addr.preind))
 	       && strcmp ("stp", inst.opcode->name) == 0)
 	{
+	  /* STP with addressing mode Pre-indexed and Base register.  */
 	  unsigned rt1 = inst.operands[0].reg.regno;
 	  unsigned rt2 = inst.operands[1].reg.regno;
 	  unsigned rn = inst.operands[2].addr.base_regno;