From patchwork Wed Jun 29 12:45:54 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 13471 Received: (qmail 56186 invoked by alias); 29 Jun 2016 12:46:25 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 56164 invoked by uid 89); 29 Jun 2016 12:46:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL, BAYES_00, GARBLED_SUBJECT, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS, UNWANTED_LANGUAGE_BODY autolearn=no version=3.3.2 spammy=Hx-languages-length:3626, 6116, watch X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Jun 2016 12:46:22 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 9679AB4D18DBE for ; Wed, 29 Jun 2016 13:46:16 +0100 (IST) Received: from pudesk170.pu.imgtec.org (192.168.93.65) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Wed, 29 Jun 2016 13:46:19 +0100 From: Bhushan Attarde To: CC: , , , , , Bhushan Attarde Subject: [PATCH 16/24] Pick msa target when appropriate and put msa registers into vector reggroups. Date: Wed, 29 Jun 2016 18:15:54 +0530 Message-ID: <1467204355-4904-3-git-send-email-bhushan.attarde@imgtec.com> In-Reply-To: <1467204355-4904-1-git-send-email-bhushan.attarde@imgtec.com> References: <1467204355-4904-1-git-send-email-bhushan.attarde@imgtec.com> MIME-Version: 1.0 gdb/ChangeLog: * mips-linux-nat.c: Include "features/mips-msa-linux.c" and "features/mips64-msa-linux.c". (mips_linux_read_description): New "have_msa" variable which is set using ptrace result and return appropriate target based on "have_msa". (initialize_tdesc_mips_msa_linux, initialize_tdesc_mips64_msa_linux): Initilizer functions for MSA targets. *mips-tdep.c (mips_register_reggroup_p): Put msa registers into vector reggroup. --- gdb/mips-linux-nat.c | 35 +++++++++++++++++++++++++++++++++-- gdb/mips-tdep.c | 4 +++- 2 files changed, 36 insertions(+), 3 deletions(-) diff --git a/gdb/mips-linux-nat.c b/gdb/mips-linux-nat.c index fd1837f..20e3d17 100644 --- a/gdb/mips-linux-nat.c +++ b/gdb/mips-linux-nat.c @@ -42,8 +42,10 @@ #include "features/mips-dsp-linux.c" #include "features/mips-fpu64-linux.c" #include "features/mips-fpu64-dsp-linux.c" +#include "features/mips-msa-linux.c" #include "features/mips64-linux.c" #include "features/mips64-dsp-linux.c" +#include "features/mips64-msa-linux.c" #ifndef PTRACE_GET_THREAD_AREA #define PTRACE_GET_THREAD_AREA 25 @@ -611,6 +613,7 @@ mips_linux_read_description (struct target_ops *ops) static int have_dsp = -1; static int have_fpu64 = -1; + static int have_msa = -1; if (have_fpu64 < 0) { @@ -631,12 +634,36 @@ mips_linux_read_description (struct target_ops *ops) break; case EIO: have_fpu64 = 0; + have_msa = 0; break; default: perror_with_name ("ptrace"); break; } } + + /* Check for MSA, which requires FR=1 */ + if (have_msa < 0) + { + int tid; + int res; + uint32_t regs[32*4 + 8]; + struct iovec iov; + + tid = ptid_get_lwp (inferior_ptid); + if (tid == 0) + tid = ptid_get_pid (inferior_ptid); + + /* this'd probably be better */ + //have_msa = (getauxval(AT_HWCAP) & 0x2) != 0; + + /* Test MSAIR */ + iov.iov_base = regs; + iov.iov_len = sizeof(regs); + res = ptrace (PTRACE_GETREGSET, tid, NT_MIPS_MSA, &iov); + have_msa = (res >= 0) && regs[32*4 + 0]; + } + if (have_dsp < 0) { int tid; @@ -664,9 +691,11 @@ mips_linux_read_description (struct target_ops *ops) /* Report that target registers are a size we know for sure that we can get from ptrace. */ if (_MIPS_SIM == _ABIO32) - return tdescs[have_dsp][have_fpu64]; + return have_msa ? tdesc_mips_msa_linux + : tdescs[have_dsp][have_fpu64]; else - return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; + return have_msa ? tdesc_mips64_msa_linux : + have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux; } /* -1 if the kernel and/or CPU do not support watch registers. @@ -1023,6 +1052,8 @@ triggers a breakpoint or watchpoint."), initialize_tdesc_mips_dsp_linux (); initialize_tdesc_mips_fpu64_linux (); initialize_tdesc_mips_fpu64_dsp_linux (); + initialize_tdesc_mips_msa_linux (); initialize_tdesc_mips64_linux (); initialize_tdesc_mips64_dsp_linux (); + initialize_tdesc_mips64_msa_linux (); } diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index a11857a..63291db 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -776,7 +776,9 @@ mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, int pseudo = regnum / gdbarch_num_regs (gdbarch); if (reggroup == all_reggroup) return pseudo; - vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); + vector_p = (TYPE_VECTOR (register_type (gdbarch, regnum)) || + rawnum == mips_regnum (gdbarch)->msa_csr || + rawnum == mips_regnum (gdbarch)->msa_ir); float_p = (mips_float_register_p (gdbarch, rawnum) || rawnum == mips_regnum (gdbarch)->fp_control_status || rawnum == mips_regnum (gdbarch)->fp_implementation_revision);