From patchwork Mon Jun 27 14:49:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhushan Attarde X-Patchwork-Id: 13398 Received: (qmail 15070 invoked by alias); 27 Jun 2016 14:51:18 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 14460 invoked by uid 89); 27 Jun 2016 14:51:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.8 required=5.0 tests=AWL, BAYES_00, GARBLED_SUBJECT, RCVD_IN_DNSWL_NONE, RP_MATCHES_RCVD, SPF_PASS autolearn=no version=3.3.2 spammy=msa, row, Large X-HELO: mailapp01.imgtec.com Received: from mailapp01.imgtec.com (HELO mailapp01.imgtec.com) (195.59.15.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 27 Jun 2016 14:51:10 +0000 Received: from hhmail02.hh.imgtec.org (unknown [10.100.10.20]) by Forcepoint Email with ESMTPS id 6BCBD8A6CEB55 for ; Mon, 27 Jun 2016 15:51:04 +0100 (IST) Received: from pudesk170.pu.imgtec.org (192.168.93.65) by hhmail02.hh.imgtec.org (10.100.10.20) with Microsoft SMTP Server (TLS) id 14.3.294.0; Mon, 27 Jun 2016 15:51:07 +0100 From: Bhushan Attarde To: CC: , , , , , Bhushan Attarde Subject: [PATCH 20/24] Drop FP and MSA control registers from default info registers Date: Mon, 27 Jun 2016 20:19:47 +0530 Message-ID: <1467038991-6600-20-git-send-email-bhushan.attarde@imgtec.com> In-Reply-To: <1467038991-6600-1-git-send-email-bhushan.attarde@imgtec.com> References: <1467038991-6600-1-git-send-email-bhushan.attarde@imgtec.com> MIME-Version: 1.0 gdb/ChangeLog: * mips-tdep.c (print_gp_register_row, mips_print_registers_info): Skip FP & MSA control registers. --- gdb/mips-tdep.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 7a6d23d..14e3aa6 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -7650,6 +7650,9 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame, if (mips_float_register_p (gdbarch, regnum) || mips_vector_register_p (gdbarch, regnum)) break; /* End the row: reached FP register. */ + if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) || + mips_register_reggroup_p (gdbarch, regnum, vector_reggroup)) + break; /* Large registers are handled separately. */ if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) { @@ -7690,6 +7693,9 @@ print_gp_register_row (struct ui_file *file, struct frame_info *frame, if (mips_float_register_p (gdbarch, regnum) || mips_vector_register_p (gdbarch, regnum)) break; /* End row: reached FP register. */ + if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) || + mips_register_reggroup_p (gdbarch, regnum, vector_reggroup)) + break; if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) break; /* End row: large register. */ @@ -7776,8 +7782,13 @@ mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, } else if (mips_register_reggroup_p (gdbarch, regnum, float_reggroup) || mips_register_reggroup_p (gdbarch, regnum, vector_reggroup)) - /* FP & MSA control registers */ - regnum = print_control_register_row (file, frame, regnum); + { + /* FP & MSA control registers */ + if (all) /* True for "INFO ALL-REGISTERS" command. */ + regnum = print_control_register_row (file, frame, regnum); + else + ++regnum; + } else regnum = print_gp_register_row (file, frame, regnum); }