diff mbox

[3/3] arm-tdep.c: Refactor arm_decode_media

Message ID 1455121027-27061-4-git-send-email-simon.marchi@ericsson.com
State New, archived
Headers

Commit Message

Simon Marchi Feb. 10, 2016, 4:17 p.m. UTC 
  Refactor arm_decode_media to make it more readable.  The new layout matches
very closely the description in the ARM Architecture Reference Manual.  It uses
the same order and same nomenclature.

gdb/ChangeLog:

	* arm-tdep.c (arm_decode_media): Refactor instruction decoding.
---
 gdb/arm-tdep.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

Comments

Yao Qi Feb. 11, 2016, 11:58 a.m. UTC | #1 
Simon Marchi <simon.marchi@ericsson.com> writes:

> -  switch (bits (insn, 20, 24))
> +  uint8_t op1 = bits (insn, 20, 24);
> +  uint8_t rd = bits (insn, 12, 15);
> +  uint8_t op2 = bits (insn, 5, 7);
> +  uint8_t rn = bits (insn, 0, 3);
> +
> +  switch (op1)

op1 is only used once, I prefer using bits (insn, 20, 24) rather than
defining a new variable.

Other variables, like rd and rn, can be defined where they are used.
diff mbox

Patch

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index e17a1a4..bf5bc49 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -6625,49 +6625,63 @@  static int
 arm_decode_media (struct gdbarch *gdbarch, uint32_t insn,
 		  struct displaced_step_closure *dsc)
 {
-  switch (bits (insn, 20, 24))
+  uint8_t op1 = bits (insn, 20, 24);
+  uint8_t rd = bits (insn, 12, 15);
+  uint8_t op2 = bits (insn, 5, 7);
+  uint8_t rn = bits (insn, 0, 3);
+
+  switch (op1)
     {
     case 0x00: case 0x01: case 0x02: case 0x03:
+      /* Parallel addition and subtraction, signed  */
       return arm_copy_unmodified (gdbarch, insn, "parallel add/sub signed", dsc);
 
     case 0x04: case 0x05: case 0x06: case 0x07:
+      /* Parallel addition and subtraction, unsigned  */
       return arm_copy_unmodified (gdbarch, insn, "parallel add/sub unsigned", dsc);
 
     case 0x08: case 0x09: case 0x0a: case 0x0b:
     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+      /* Packing, unpacking, saturation, and reversal  */
       return arm_copy_unmodified (gdbarch, insn,
 			      "decode/pack/unpack/saturate/reverse", dsc);
 
     case 0x18:
-      if (bits (insn, 5, 7) == 0)  /* op2.  */
+      if (op2 == 0)
 	 {
-	  if (bits (insn, 12, 15) == 0xf)
+	  if (rd == 0xf)
+	    /* USAD8  */
 	    return arm_copy_unmodified (gdbarch, insn, "usad8", dsc);
 	  else
+	    /* USADA8  */
 	    return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
 	}
       else
-	 return arm_copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1a: case 0x1b:
-      if (bits (insn, 5, 6) == 0x2)  /* op2[1:0].  */
+      if ((op2 & 0x3) == 0x2)
+	/* SBFX  */
 	return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
       else
 	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1c: case 0x1d:
-      if (bits (insn, 5, 6) == 0x0)  /* op2[1:0].  */
+      if ((op2 & 0x3) == 0x0)
 	 {
-	  if (bits (insn, 0, 3) == 0xf)
+	  if (rn == 0xf)
+	    /* BFC  */
 	    return arm_copy_unmodified (gdbarch, insn, "bfc", dsc);
 	  else
+	    /* BFI  */
 	    return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
 	}
       else
 	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1e: case 0x1f:
-      if (bits (insn, 5, 6) == 0x2)  /* op2[1:0].  */
+      if ((op2 & 0x3) == 0x2)
+	/* UBFX  */
 	return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
       else
 	return arm_copy_undef (gdbarch, insn, dsc);