From patchwork Wed Feb 10 16:17:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 10797 Received: (qmail 101947 invoked by alias); 10 Feb 2016 16:17:31 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 101870 invoked by uid 89); 10 Feb 2016 16:17:31 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00, SPF_PASS autolearn=ham version=3.3.2 spammy=miscellaneous, synch, 0x02, imm X-HELO: usplmg21.ericsson.net Received: from usplmg21.ericsson.net (HELO usplmg21.ericsson.net) (198.24.6.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 10 Feb 2016 16:17:24 +0000 Received: from EUSAAHC002.ericsson.se (Unknown_Domain [147.117.188.78]) by usplmg21.ericsson.net (Symantec Mail Security) with SMTP id F3.39.32102.A726BB65; Wed, 10 Feb 2016 17:16:58 +0100 (CET) Received: from elxcz23q12-y4.dyn.mo.ca.am.ericsson.se (147.117.188.8) by smtps-am.internal.ericsson.com (147.117.188.78) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 10 Feb 2016 11:17:14 -0500 From: Simon Marchi To: CC: Simon Marchi Subject: [PATCH 2/3] arm-tdep.c: Refactor arm_decode_dp_misc Date: Wed, 10 Feb 2016 11:17:06 -0500 Message-ID: <1455121027-27061-3-git-send-email-simon.marchi@ericsson.com> In-Reply-To: <1455121027-27061-1-git-send-email-simon.marchi@ericsson.com> References: <1455121027-27061-1-git-send-email-simon.marchi@ericsson.com> MIME-Version: 1.0 X-IsSubscribed: yes Refactor arm_decode_dp_misc to make it more readable. The new layout matches very closely the description in the ARM Architecture Reference Manual. It uses the same order and same nomenclature. gdb/ChangeLog: * arm-tdep.c (arm_decode_dp_misc): Refactor instruction decoding. --- gdb/arm-tdep.c | 73 +++++++++++++++++++++++++++++++++++++++------------------- 1 file changed, 49 insertions(+), 24 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 0a9c0f6..e17a1a4 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -6517,45 +6517,70 @@ arm_decode_dp_misc (struct gdbarch *gdbarch, uint32_t insn, struct regcache *regs, struct displaced_step_closure *dsc) { - if (bit (insn, 25)) - switch (bits (insn, 20, 24)) - { - case 0x10: - return arm_copy_unmodified (gdbarch, insn, "movw", dsc); - - case 0x14: - return arm_copy_unmodified (gdbarch, insn, "movt", dsc); + uint8_t op = bit (insn, 25); + uint8_t op1 = bits (insn, 20, 24); + uint8_t op2 = bits (insn, 4, 7); - case 0x12: case 0x16: - return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); - - default: - return arm_copy_alu_imm (gdbarch, insn, regs, dsc); - } - else + if (op == 0) { - uint32_t op1 = bits (insn, 20, 24), op2 = bits (insn, 4, 7); - if ((op1 & 0x19) != 0x10 && (op2 & 0x1) == 0x0) + /* Data-processing (register) */ return arm_copy_alu_reg (gdbarch, insn, regs, dsc); else if ((op1 & 0x19) != 0x10 && (op2 & 0x9) == 0x1) + /* Data-processing (register-shifted register) */ return arm_copy_alu_shifted_reg (gdbarch, insn, regs, dsc); else if ((op1 & 0x19) == 0x10 && (op2 & 0x8) == 0x0) + /* Miscellaneous instructions */ return arm_decode_miscellaneous (gdbarch, insn, regs, dsc); else if ((op1 & 0x19) == 0x10 && (op2 & 0x9) == 0x8) + /* Halfword multiply and multiply accumulate */ return arm_copy_unmodified (gdbarch, insn, "halfword mul/mla", dsc); else if ((op1 & 0x10) == 0x00 && op2 == 0x9) + /* Multiply and multiply accumulate */ return arm_copy_unmodified (gdbarch, insn, "mul/mla", dsc); else if ((op1 & 0x10) == 0x10 && op2 == 0x9) + /* Synchronization primitives */ return arm_copy_unmodified (gdbarch, insn, "synch", dsc); - else if (op2 == 0xb || (op2 & 0xd) == 0xd) - /* 2nd arg means "unprivileged". */ - return arm_copy_extra_ld_st (gdbarch, insn, (op1 & 0x12) == 0x02, regs, - dsc); + else if ((op1 & 0x12) != 0x2 && op2 == 0xb) + /* Extra load/store instructions */ + return arm_copy_extra_ld_st (gdbarch, insn, 0, regs, dsc); + else if ((op1 & 0x12) != 0x2 && (op2 & 0xd) == 0xd) + /* Extra load/store instructions */ + return arm_copy_extra_ld_st (gdbarch, insn, 0, regs, dsc); + else if ((op1 & 0x13) == 0x2 && (op2 & 0xd) == 0xd) + /* Extra load/store instructions */ + return arm_copy_extra_ld_st (gdbarch, insn, 0, regs, dsc); + else if ((op1 & 0x12) == 0x2 && op2 == 0xd) + /* Extra load/store instructions, unprivileged */ + return arm_copy_extra_ld_st (gdbarch, insn, 1, regs, dsc); + else if ((op1 & 0x13) == 0x3 && (op2 & 0xd) == 0xd) + /* Extra load/store instructions, unprivileged */ + return arm_copy_extra_ld_st (gdbarch, insn, 1, regs, dsc); + else + return 1; + } + else + { + switch (op1) + { + default: + /* Data-processing (immediate) */ + return arm_copy_alu_imm (gdbarch, insn, regs, dsc); + + case 0x10: + /* 16-bit immediate load, MOV (immediate) */ + return arm_copy_unmodified (gdbarch, insn, "movw", dsc); + + case 0x14: + /* High halfword 16-bit immediate load, MOVT */ + return arm_copy_unmodified (gdbarch, insn, "movt", dsc); + + case 0x12: + case 0x16: + /* MSR (immediate), and hints */ + return arm_copy_unmodified (gdbarch, insn, "msr imm", dsc); + } } - - /* Should be unreachable. */ - return 1; } static int