From patchwork Wed Feb 10 16:17:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 10796 Received: (qmail 100933 invoked by alias); 10 Feb 2016 16:17:24 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 100846 invoked by uid 89); 10 Feb 2016 16:17:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 spammy=displaced, Supervisor, miscellaneous, Hx-languages-length:2956 X-HELO: usplmg21.ericsson.net Received: from usplmg21.ericsson.net (HELO usplmg21.ericsson.net) (198.24.6.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Wed, 10 Feb 2016 16:17:22 +0000 Received: from EUSAAHC002.ericsson.se (Unknown_Domain [147.117.188.78]) by usplmg21.ericsson.net (Symantec Mail Security) with SMTP id 92.39.32102.9726BB65; Wed, 10 Feb 2016 17:16:58 +0100 (CET) Received: from elxcz23q12-y4.dyn.mo.ca.am.ericsson.se (147.117.188.8) by smtps-am.internal.ericsson.com (147.117.188.78) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 10 Feb 2016 11:17:14 -0500 From: Simon Marchi To: CC: Simon Marchi Subject: [PATCH 1/3] arm-tdep.c: Refactor arm_process_displaced_insn Date: Wed, 10 Feb 2016 11:17:05 -0500 Message-ID: <1455121027-27061-2-git-send-email-simon.marchi@ericsson.com> In-Reply-To: <1455121027-27061-1-git-send-email-simon.marchi@ericsson.com> References: <1455121027-27061-1-git-send-email-simon.marchi@ericsson.com> MIME-Version: 1.0 X-IsSubscribed: yes Refactor arm_process_displaced_insn to make it more readable. The new layout matches very closely the description in the ARM Architecture Reference Manual. It uses the same order and same nomenclature. gdb/ChangeLog: * arm-tdep.c (arm_process_displaced_insn): Refactor instruction decoding. --- gdb/arm-tdep.c | 68 ++++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 50 insertions(+), 18 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 6ac05f0..0a9c0f6 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -7495,6 +7495,7 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, int err = 0; enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); uint32_t insn; + uint8_t cond, op, op1; /* Most displaced instructions use a 1-instruction scratch space, so set this here and override below if/when necessary. */ @@ -7515,29 +7516,60 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, "at %.8lx\n", (unsigned long) insn, (unsigned long) from); - if ((insn & 0xf0000000) == 0xf0000000) - err = arm_decode_unconditional (gdbarch, insn, regs, dsc); - else switch (((insn & 0x10) >> 4) | ((insn & 0xe000000) >> 24)) + cond = bits (insn, 28, 31); + op1 = bits (insn, 25, 27); + op = bit (insn, 4); + + if (cond != 0xf) { - case 0x0: case 0x1: case 0x2: case 0x3: - err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); - break; + switch (op1) + { + case 0x0: + case 0x1: + /* Data-processing and miscellaneous instructions */ + err = arm_decode_dp_misc (gdbarch, insn, regs, dsc); + break; - case 0x4: case 0x5: case 0x6: - err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); - break; + case 0x2: + /* Load/store word and unsigned byte */ + err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); + break; - case 0x7: - err = arm_decode_media (gdbarch, insn, dsc); - break; + case 0x3: + if (op == 0) + { + /* Load/store word and unsigned byte */ + err = arm_decode_ld_st_word_ubyte (gdbarch, insn, regs, dsc); + } + else + { + /* Media instructions */ + err = arm_decode_media (gdbarch, insn, dsc); + } + break; - case 0x8: case 0x9: case 0xa: case 0xb: - err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); - break; + case 0x4: + case 0x5: + /* Branch, branch with link, and block data transfer */ + err = arm_decode_b_bl_ldmstm (gdbarch, insn, regs, dsc); + break; - case 0xc: case 0xd: case 0xe: case 0xf: - err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc); - break; + case 0x6: + case 0x7: + /* Coprocessor instructions, and Supervisor Call */ + err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc); + break; + + default: + internal_error (__FILE__, __LINE__, + _("arm_process_displaced_insn: Missing case")); + break; + } + } + else + { + /* Unconditional instructions */ + err = arm_decode_unconditional (gdbarch, insn, regs, dsc); } if (err)