From patchwork Sun Dec 27 08:51:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 10148 Received: (qmail 119131 invoked by alias); 27 Dec 2015 08:51:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 119118 invoked by uid 89); 27 Dec 2015 08:51:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.8 required=5.0 tests=AWL, BAYES_50, RCVD_IN_DNSWL_LOW, SPF_SOFTFAIL autolearn=no version=3.3.2 spammy=20.0, 174, 90, 0x1000 X-HELO: mail2.asahi-net.or.jp Received: from mail2.asahi-net.or.jp (HELO mail2.asahi-net.or.jp) (202.224.39.198) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 27 Dec 2015 08:51:44 +0000 Received: from sa76r4 (y081184.ppp.asahi-net.or.jp [118.243.81.184]) by mail2.asahi-net.or.jp (Postfix) with ESMTP id 10590B897; Sun, 27 Dec 2015 17:51:41 +0900 (JST) Received: from localhost (localhost [127.0.0.1]) by sa76r4 (Postfix) with ESMTP id 0C83DE885; Sun, 27 Dec 2015 17:51:41 +0900 (JST) Received: from sa76r4 ([127.0.0.1]) by localhost (sa76r4.localdomain [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MRclBv3E9nzy; Sun, 27 Dec 2015 17:51:40 +0900 (JST) Received: by sa76r4 (Postfix, from userid 1000) id D2FA0105E2; Sun, 27 Dec 2015 17:51:40 +0900 (JST) From: Yoshinori Sato To: gdb-patches@sourceware.org Cc: Yoshinori Sato Subject: [PATCH][RX] instructions test set.. Date: Sun, 27 Dec 2015 17:51:30 +0900 Message-Id: <1451206290-14327-2-git-send-email-ysato@users.sourceforge.jp> In-Reply-To: <1451206290-14327-1-git-send-email-ysato@users.sourceforge.jp> References: <1451206290-14327-1-git-send-email-ysato@users.sourceforge.jp> X-IsSubscribed: yes --- sim/testsuite/sim/rx/ChangeLog | 11 ++ sim/testsuite/sim/rx/abs.s | 25 +++ sim/testsuite/sim/rx/adc.s | 77 ++++++++++ sim/testsuite/sim/rx/add.s | 108 +++++++++++++ sim/testsuite/sim/rx/allinsn.exp | 25 +++ sim/testsuite/sim/rx/and.s | 79 ++++++++++ sim/testsuite/sim/rx/bcnd.s | 60 ++++++++ sim/testsuite/sim/rx/bmcnd.s | 132 ++++++++++++++++ sim/testsuite/sim/rx/bra.s | 23 +++ sim/testsuite/sim/rx/bset.s | 197 ++++++++++++++++++++++++ sim/testsuite/sim/rx/cmp.s | 74 +++++++++ sim/testsuite/sim/rx/div.s | 52 +++++++ sim/testsuite/sim/rx/emaca.s | 24 +++ sim/testsuite/sim/rx/emsba.s | 24 +++ sim/testsuite/sim/rx/emul.s | 92 +++++++++++ sim/testsuite/sim/rx/emula.s | 24 +++ sim/testsuite/sim/rx/fadd.s | 41 +++++ sim/testsuite/sim/rx/fcmp.s | 37 +++++ sim/testsuite/sim/rx/fdiv.s | 43 ++++++ sim/testsuite/sim/rx/fmul.s | 51 +++++++ sim/testsuite/sim/rx/fsqrt.s | 23 +++ sim/testsuite/sim/rx/fsub.s | 51 +++++++ sim/testsuite/sim/rx/ftoi.s | 37 +++++ sim/testsuite/sim/rx/ftou.s | 37 +++++ sim/testsuite/sim/rx/itof.s | 37 +++++ sim/testsuite/sim/rx/jmp.s | 12 ++ sim/testsuite/sim/rx/machilo.s | 53 +++++++ sim/testsuite/sim/rx/max.s | 45 ++++++ sim/testsuite/sim/rx/min.s | 45 ++++++ sim/testsuite/sim/rx/mov.s | 196 ++++++++++++++++++++++++ sim/testsuite/sim/rx/movlico.s | 22 +++ sim/testsuite/sim/rx/movu.s | 67 ++++++++ sim/testsuite/sim/rx/msbhilo.s | 43 ++++++ sim/testsuite/sim/rx/mul.s | 52 +++++++ sim/testsuite/sim/rx/mulhilo.s | 54 +++++++ sim/testsuite/sim/rx/mvacc.s | 28 ++++ sim/testsuite/sim/rx/mvftc.s | 36 +++++ sim/testsuite/sim/rx/neg.s | 17 +++ sim/testsuite/sim/rx/not.s | 17 +++ sim/testsuite/sim/rx/or.s | 69 +++++++++ sim/testsuite/sim/rx/pushpop.s | 48 ++++++ sim/testsuite/sim/rx/racw.s | 38 +++++ sim/testsuite/sim/rx/rdacw.s | 19 +++ sim/testsuite/sim/rx/rev.s | 14 ++ sim/testsuite/sim/rx/rmpa.s | 23 +++ sim/testsuite/sim/rx/rot.s | 46 ++++++ sim/testsuite/sim/rx/round.s | 37 +++++ sim/testsuite/sim/rx/sat.s | 37 +++++ sim/testsuite/sim/rx/sbb.s | 46 ++++++ sim/testsuite/sim/rx/sccnd.s | 169 +++++++++++++++++++++ sim/testsuite/sim/rx/scmpu.s | 26 ++++ sim/testsuite/sim/rx/shlr.s | 67 ++++++++ sim/testsuite/sim/rx/smovb.s | 53 +++++++ sim/testsuite/sim/rx/smovu.s | 23 +++ sim/testsuite/sim/rx/sstr.s | 44 ++++++ sim/testsuite/sim/rx/stz.s | 52 +++++++ sim/testsuite/sim/rx/sub.s | 53 +++++++ sim/testsuite/sim/rx/suntil.s | 59 ++++++++ sim/testsuite/sim/rx/testutils.inc | 302 +++++++++++++++++++++++++++++++++++++ sim/testsuite/sim/rx/tst.s | 54 +++++++ sim/testsuite/sim/rx/utof.s | 37 +++++ sim/testsuite/sim/rx/xchg.s | 36 +++++ sim/testsuite/sim/rx/xor.s | 58 +++++++ 63 files changed, 3481 insertions(+) create mode 100644 sim/testsuite/sim/rx/ChangeLog create mode 100644 sim/testsuite/sim/rx/abs.s create mode 100644 sim/testsuite/sim/rx/adc.s create mode 100644 sim/testsuite/sim/rx/add.s create mode 100644 sim/testsuite/sim/rx/allinsn.exp create mode 100644 sim/testsuite/sim/rx/and.s create mode 100644 sim/testsuite/sim/rx/bcnd.s create mode 100644 sim/testsuite/sim/rx/bmcnd.s create mode 100644 sim/testsuite/sim/rx/bra.s create mode 100644 sim/testsuite/sim/rx/bset.s create mode 100644 sim/testsuite/sim/rx/cmp.s create mode 100644 sim/testsuite/sim/rx/div.s create mode 100644 sim/testsuite/sim/rx/emaca.s create mode 100644 sim/testsuite/sim/rx/emsba.s create mode 100644 sim/testsuite/sim/rx/emul.s create mode 100644 sim/testsuite/sim/rx/emula.s create mode 100644 sim/testsuite/sim/rx/fadd.s create mode 100644 sim/testsuite/sim/rx/fcmp.s create mode 100644 sim/testsuite/sim/rx/fdiv.s create mode 100644 sim/testsuite/sim/rx/fmul.s create mode 100644 sim/testsuite/sim/rx/fsqrt.s create mode 100644 sim/testsuite/sim/rx/fsub.s create mode 100644 sim/testsuite/sim/rx/ftoi.s create mode 100644 sim/testsuite/sim/rx/ftou.s create mode 100644 sim/testsuite/sim/rx/itof.s create mode 100644 sim/testsuite/sim/rx/jmp.s create mode 100644 sim/testsuite/sim/rx/machilo.s create mode 100644 sim/testsuite/sim/rx/max.s create mode 100644 sim/testsuite/sim/rx/min.s create mode 100644 sim/testsuite/sim/rx/mov.s create mode 100644 sim/testsuite/sim/rx/movlico.s create mode 100644 sim/testsuite/sim/rx/movu.s create mode 100644 sim/testsuite/sim/rx/msbhilo.s create mode 100644 sim/testsuite/sim/rx/mul.s create mode 100644 sim/testsuite/sim/rx/mulhilo.s create mode 100644 sim/testsuite/sim/rx/mvacc.s create mode 100644 sim/testsuite/sim/rx/mvftc.s create mode 100644 sim/testsuite/sim/rx/neg.s create mode 100644 sim/testsuite/sim/rx/not.s create mode 100644 sim/testsuite/sim/rx/or.s create mode 100644 sim/testsuite/sim/rx/pushpop.s create mode 100644 sim/testsuite/sim/rx/racw.s create mode 100644 sim/testsuite/sim/rx/rdacw.s create mode 100644 sim/testsuite/sim/rx/rev.s create mode 100644 sim/testsuite/sim/rx/rmpa.s create mode 100644 sim/testsuite/sim/rx/rot.s create mode 100644 sim/testsuite/sim/rx/round.s create mode 100644 sim/testsuite/sim/rx/sat.s create mode 100644 sim/testsuite/sim/rx/sbb.s create mode 100644 sim/testsuite/sim/rx/sccnd.s create mode 100644 sim/testsuite/sim/rx/scmpu.s create mode 100644 sim/testsuite/sim/rx/shlr.s create mode 100644 sim/testsuite/sim/rx/smovb.s create mode 100644 sim/testsuite/sim/rx/smovu.s create mode 100644 sim/testsuite/sim/rx/sstr.s create mode 100644 sim/testsuite/sim/rx/stz.s create mode 100644 sim/testsuite/sim/rx/sub.s create mode 100644 sim/testsuite/sim/rx/suntil.s create mode 100644 sim/testsuite/sim/rx/testutils.inc create mode 100644 sim/testsuite/sim/rx/tst.s create mode 100644 sim/testsuite/sim/rx/utof.s create mode 100644 sim/testsuite/sim/rx/xchg.s create mode 100644 sim/testsuite/sim/rx/xor.s diff --git a/sim/testsuite/sim/rx/ChangeLog b/sim/testsuite/sim/rx/ChangeLog new file mode 100644 index 0000000..d149e6a --- /dev/null +++ b/sim/testsuite/sim/rx/ChangeLog @@ -0,0 +1,11 @@ +2015-12-27 Yoshinori Sato + + * abs.s, adc.s, add.s, and.s, bcnd.s, bmcnd.s, bra.s, bset.s, + cmp.s, div.s, emaca.s, emsba.s, emul.s, emula.s, fadd.s, fcmp.s, + fdiv.s, fmul.s, fsqrt.s, fsub.s, ftoi.s, ftou.s, itof.s, jmp.s, + machilo.s, max.s, min.s, mov.s, movlico.s, movu.s, msbhilo.s, + mul.s, mulhilo.s, mvacc.s, mvftc.s, neg.s, not.s, or.s,pushpop.s, + racw.s, rdacw.s, rev.s, rmpa.s, rot.s, round.s, sbb.s, sccnd.s, + scmpu.s, shlr.s, smovb.s, smovu.s, sstr.s, stz.s, sub.s, suntil.s, + tst.s,utof.s,xchg.s,xor.s: New file. + * allinsn.exp: New file. diff --git a/sim/testsuite/sim/rx/abs.s b/sim/testsuite/sim/rx/abs.s new file mode 100644 index 0000000..3747797 --- /dev/null +++ b/sim/testsuite/sim/rx/abs.s @@ -0,0 +1,25 @@ +# RX testcase for abs +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +abs_dest: + mov.l #1,r1 + abs r1 + test_h_gr32 1 r1 + mov.l #-1,r1 + abs r1 + test_h_gr32 1 r1 +abs_src_dest: + sub r2,r2 + mov.l #1,r1 + abs r1,r2 + test_h_gr32 1 r2 + sub r2,r2 + mov.l #-1,r1 + abs r1,r2 + test_h_gr32 1 r2 + + pass diff --git a/sim/testsuite/sim/rx/adc.s b/sim/testsuite/sim/rx/adc.s new file mode 100644 index 0000000..49a8a6e --- /dev/null +++ b/sim/testsuite/sim/rx/adc.s @@ -0,0 +1,77 @@ +# RX testcase for adc +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +adc_imm4: + clear_carry_flag + mov.l #1,r1 + adc #2,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 3 r1 +adc_imm8: + clear_carry_flag + adc #-1,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 2 r1 +adc_imm16: + set_carry_flag + adc #0x7ffd,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x8000 r1 +adc_imm24: + clear_carry_flag + adc #0x800000 - 0x8000,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x800000 r1 +adc_imm32: + clear_carry_flag + adc #0x80000000 - 0x800000,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_h_gr32 0x80000000 r1 +adc_reg: + clear_carry_flag + mov.l #0x80000000,r2 + adc r2,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +adc_mem_ind: + mov.l #val, r2 + adc [r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 2 r1 +adc_mem_dsp8: + mov.l #val-4, r2 + adc 4[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 4 r1 +adc_mem_dsp16: + mov.l #val-0x1000, r2 + adc 0x1000[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 6 r1 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/add.s b/sim/testsuite/sim/rx/add.s new file mode 100644 index 0000000..a483d01 --- /dev/null +++ b/sim/testsuite/sim/rx/add.s @@ -0,0 +1,108 @@ +# RX testcase for add +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +add_imm4: + mov.l #1,r1 + add #2,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 3 r1 +add_imm8: + add #-1,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 2 r1 +add_imm16: + add #0x7ffe,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x8000 r1 +add_imm24: + add #0x800000 - 0x8000,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x800000 r1 +add_imm32: + add #0x80000000 - 0x800000,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_h_gr32 0x80000000 r1 +add_reg: + mov.l #0x80000000,r2 + add r2,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +add_mem_ind: + mov.l #val, r2 + add [r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 1 r1 +add_mem_dsp8: + mov.l #val-4, r2 + add 4[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 2 r1 +add_mem_dsp16: + mov.l #val-0x1000, r2 + add 0x1000[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 3 r1 +add3_imm4: + mov.l #1,r1 + add #2,r1,r2 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 3 r2 +add3_imm8: + add #-1,r1,r2 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r2 +add3_imm16: + add #0x7ffe,r1,r2 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x7fff r2 +add3_imm24: + add #0x7ffffe,r1,r2 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x7fffff r2 +add3_imm32: + add #0x7ffffffe,r1,r2 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 0x7fffffff r2 +add3_reg: + add r1,r1,r2 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 2 r2 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/allinsn.exp b/sim/testsuite/sim/rx/allinsn.exp new file mode 100644 index 0000000..e566c62 --- /dev/null +++ b/sim/testsuite/sim/rx/allinsn.exp @@ -0,0 +1,25 @@ +# Renesas RX simulator testsuite + +if [istarget rx-*-*] { + set global_ld_options "-Ttext=0x01000000 --defsym __stack=0x01800000" + + set mach "rx" + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $mach + } + + set mach "rxv2" + foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] { + # If we're only testing specific files and this isn't one of them, + # skip it. + if ![runtest_file_p $runtests $src] { + continue + } + run_sim_test $src $mach + } +} diff --git a/sim/testsuite/sim/rx/and.s b/sim/testsuite/sim/rx/and.s new file mode 100644 index 0000000..4044562 --- /dev/null +++ b/sim/testsuite/sim/rx/and.s @@ -0,0 +1,79 @@ +# RX testcase for and +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +and_imm4: + mov.l #2,r1 + and #2,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_h_gr32 2 r1 +and_imm8: + and #0x13,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 2 r1 +and_imm16: + and #0xffff,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 2 r1 +and_imm24: + and #0xffffff,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 2 r1 +and_imm32: + mov.l #0x80000000,r1 + and #0xffffffff,r1 + test_zero_clear + test_carry_set + test_neg_set + test_h_gr32 0x80000000 r1 +and_reg: + mov.l #0x80000000,r2 + and r2,r1 + test_zero_clear + test_carry_set + test_neg_set + test_h_gr32 0x80000000 r1 +and_mem_ind: + mov.l #val, r2 + and [r2].l,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +and_mem_dsp8: + mov.l #val-4, r2 + and 4[r2].l,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +and_mem_dsp16: + mov.l #val-0x1000, r2 + and 0x1000[r2].l,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +and3_reg: + mov.l #0x80000000,r2 + and r2,r1,r3 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r3 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/bcnd.s b/sim/testsuite/sim/rx/bcnd.s new file mode 100644 index 0000000..769c4b8 --- /dev/null +++ b/sim/testsuite/sim/rx/bcnd.s @@ -0,0 +1,60 @@ +# RX testcase for Bcnd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + sub r2,r2 + set_zero_flag + beq.s 1f + add #1,r2 +1: clear_zero_flag + bne.s 2f + add #1,r2 +2: test_h_gr32 0 r2 + mov #10,r1 + cmp #5,r1 + bc 3f + fail +3: cmp #15,r1 + bnc 4f + fail +4: mov #-5,r1 + cmp #-10,r1 + bgt 5f + fail +5: cmp #-5,r1 + ble 6f + fail +6: bge 7f + fail +7: cmp #-1,r1 + blt 8f + fail +8: mov.l #0xc0000000,r1 + cmp #0x80000000,r1 + bgtu 9f + fail +9: mov #1,r1 + tst r1,r1 + bpz 11f + fail +11: mov #-1,r1 + tst r1,r1 + bn 12f + fail +12: set_overflow_flag + bo 13f + fail +13: clear_overflow_flag + bno 14f + fail +14: set_zero_flag + beq.w 15f + fail +15: clear_zero_flag + bne.w 16f + fail +16: + pass diff --git a/sim/testsuite/sim/rx/bmcnd.s b/sim/testsuite/sim/rx/bmcnd.s new file mode 100644 index 0000000..f3059eb --- /dev/null +++ b/sim/testsuite/sim/rx/bmcnd.s @@ -0,0 +1,132 @@ +# RX testcase for BMcnd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #val,r2 + mov #val-4,r3 + mov #val-0x1000,r4 + mov #10,r1 + cmp #5,r1 + bmc #0,[r2].b + bmc #1,4[r3].b + bmc #2,0x1000[r4].b + bmc #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + cmp #15,r1 + bmnc #0,[r2].b + bmnc #1,4[r3].b + bmnc #2,0x1000[r4].b + bmnc #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #-5,r1 + cmp #-10,r1 + bmgt #0,[r2].b + bmgt #1,4[r3].b + bmgt #2,0x1000[r4].b + bmgt #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #-5,r1 + cmp #-5,r1 + bmle #0,[r2].b + bmle #1,4[r3].b + bmle #2,0x1000[r4].b + bmle #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #-5,r1 + cmp #-5,r1 + bmge #0,[r2].b + bmge #1,4[r3].b + bmge #2,0x1000[r4].b + bmge #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #-5,r1 + cmp #-1,r1 + bmlt #0,[r2].b + bmlt #1,4[r3].b + bmlt #2,0x1000[r4].b + bmlt #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov.l #0xc0000000,r1 + cmp #0x80000000,r1 + bmgtu #0,[r2].b + bmgtu #1,4[r3].b + bmgtu #2,0x1000[r4].b + bmgtu #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #1,r1 + tst r1,r1 + bmpz #0,[r2].b + bmpz #1,4[r3].b + bmpz #2,0x1000[r4].b + bmpz #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + mov #-1,r1 + tst r1,r1 + bmn #0,[r2].b + bmn #1,4[r3].b + bmn #2,0x1000[r4].b + bmn #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + set_overflow_flag + bmo #0,[r2].b + bmo #1,4[r3].b + bmo #2,0x1000[r4].b + bmo #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + mov.b #0,[r2] + clear_overflow_flag + bmno #0,[r2].b + bmno #1,4[r3].b + bmno #2,0x1000[r4].b + bmno #0,r5 + btst #0,r5 + test_zero_clear + mov.b [r2],r5 + test_h_gr32 7 r5 + + pass + + .data +val: .byte 0 diff --git a/sim/testsuite/sim/rx/bra.s b/sim/testsuite/sim/rx/bra.s new file mode 100644 index 0000000..443d4db --- /dev/null +++ b/sim/testsuite/sim/rx/bra.s @@ -0,0 +1,23 @@ +# RX testcase for bra +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + sub r2,r2 + bra.s 1f + add #1,r2 +1: test_h_gr32 0 r2 + bra.b 2f + fail +2: bra.w 3f + fail +3: bra.a 4f + fail +4: mov #6f,r1 + sub #5f,r1 +5: bra r1 + fail +6: + pass diff --git a/sim/testsuite/sim/rx/bset.s b/sim/testsuite/sim/rx/bset.s new file mode 100644 index 0000000..69c6e21 --- /dev/null +++ b/sim/testsuite/sim/rx/bset.s @@ -0,0 +1,197 @@ +# RX testcase for bset/bclr/bnot/btst +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +bset_imm_ind: + mov.l #val,r2 + bset #0,[r2].b + btst #0,[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bclr_imm_ind: + bclr #1,[r2].b + btst #1,[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 1 r1 +bnot_imm_ind: + bnot #1,[r2].b + btst #1,[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bset_imm_dsp8: + mov.l #val-4,r2 + bset #2,4[r2].b + btst #2,4[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bclr_imm_dsp8: + bclr #2,4[r2].b + btst #2,4[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bnot_imm_dsp8: + bnot #2,4[r2].b + btst #2,4[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bset_imm_dsp16: + mov.l #val-0x1000,r2 + bset #2,0x1000[r2].b + btst #2,0x1000[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bclr_imm_dsp16: + bclr #2,0x1000[r2].b + btst #2,0x1000[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bnot_imm_dsp16: + bnot #2,0x1000[r2].b + btst #2,0x1000[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bset_reg_ind: + mov.l #0,r1 + mov.l #val,r2 + bset r1,[r2].b + btst r1,[r2].b + test_zero_clear + test_carry_set + mov.b [r2],r1 + test_h_gr32 7 r1 +bclr_reg_ind: + mov.l #0,r1 + bclr r1,[r2].b + btst r1,[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 6 r1 +bnot_reg_ind: + mov.l #0,r1 + bnot r1,[r2].b + btst r1,[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bset_reg_dsp8: + mov.l #2,r1 + mov.l #val-4,r2 + bset r1,4[r2].b + btst r1,4[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bclr_reg_dsp8: + mov.l #2,r1 + bclr r1,4[r2].b + btst r1,4[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bnot_reg_dsp8: + mov.l #2,r1 + bnot r1,4[r2].b + btst r1,4[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bset_reg_dsp16: + mov.l #2,r1 + mov.l #val-0x1000,r2 + bset r1,0x1000[r2].b + btst r1,0x1000[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bclr_reg_dsp16: + mov.l #2,r1 + bclr r1,0x1000[r2].b + btst r1,0x1000[r2].b + test_zero_set + test_carry_clear + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 3 r1 +bnot_reg_dsp16: + mov.l #2,r1 + bnot r1,0x1000[r2].b + btst r1,0x1000[r2].b + test_zero_clear + test_carry_set + mov.l #val,r1 + mov.b [r1],r1 + test_h_gr32 7 r1 +bnot_imm_reg: + sub r1,r1 + bnot #1,r1 + btst #1,r1 + test_zero_clear + test_carry_set + test_h_gr32 2 r1 +bset_reg_reg: + sub r1,r1 + mov.l #1,r2 + bset r2,r1 + btst r2,r1 + test_zero_clear + test_carry_set + test_h_gr32 2 r1 +bclr_reg_reg: + bclr r2,r1 + btst r2,r1 + test_zero_set + test_carry_clear + test_h_gr32 0 r1 +bnot_reg_reg: + bnot r2,r1 + btst r2,r1 + test_zero_clear + test_carry_set + test_h_gr32 2 r1 + + pass + + .data +val: .byte 2 diff --git a/sim/testsuite/sim/rx/cmp.s b/sim/testsuite/sim/rx/cmp.s new file mode 100644 index 0000000..73dff9d --- /dev/null +++ b/sim/testsuite/sim/rx/cmp.s @@ -0,0 +1,74 @@ +# RX testcase for cmp +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +cmp_imm4: + mov #1,r1 + cmp #2,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_overflow_clear +cmp_imm8: + cmp #-1,r1 + test_zero_clear + test_carry_clear + test_neg_clear + test_overflow_clear +cmp_imm16: + mov #0x8000,r1 + cmp #0x8000,r1 + test_zero_set + test_carry_set + test_neg_clear + test_overflow_clear +cmp_imm24: + mov #0x800000,r1 + cmp #0x7fffff,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_overflow_clear +cmp_imm32: + mov #0x80000000,r1 + cmp #0x7fffffff,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_overflow_set +cmp_reg: + mov.l #0x80000000,r2 + cmp r2,r1 + test_zero_set + test_carry_set + test_neg_clear +cmp_mem_ind: + sub r1,r1 + mov #val, r2 + cmp [r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_overflow_clear +cmp_mem_dsp8: + mov #val-4, r2 + cmp 4[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_overflow_clear +cmp_mem_dsp16: + mov #val-0x1000, r2 + cmp 0x1000[r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_overflow_clear + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/div.s b/sim/testsuite/sim/rx/div.s new file mode 100644 index 0000000..40b814d --- /dev/null +++ b/sim/testsuite/sim/rx/div.s @@ -0,0 +1,52 @@ +# RX testcase for div/divu +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +div_imm8: + mov #2,r1 + div #2,r1 + test_h_gr32 1 r1 +div_imm16: + mov #0x8000,r1 + div #0x1000,r1 + test_h_gr32 8 r1 +div_imm24: + mov #0x800000,r1 + div #0x200000,r1 + test_h_gr32 4 r1 +div_imm32: + mov #0x80000000,r1 + div #0x40000000,r1 + test_h_gr32 -2 r1 +divu_imm32: + mov #0x80000000,r1 + divu #0x40000000,r1 + test_h_gr32 2 r1 +div_reg: + mov #0x80000000,r1 + mov r1,r2 + div r2,r1 + test_h_gr32 1 r1 +div_mem_ind: + mov #10,r1 + mov #val, r2 + div [r2],r1 + test_h_gr32 5 r1 +div_mem_dsp8: + mov #10,r1 + mov #val-4, r2 + div 4[r2],r1 + test_h_gr32 5 r1 +div_mem_dsp16: + mov #10,r1 + mov #val-0x1000, r2 + div 0x1000[r2],r1 + test_h_gr32 5 r1 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/emaca.s b/sim/testsuite/sim/rx/emaca.s new file mode 100644 index 0000000..e066d57 --- /dev/null +++ b/sim/testsuite/sim/rx/emaca.s @@ -0,0 +1,24 @@ +# RX testcase for emaca +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #100, r1 + mov #200, r2 + emaca r1,r2,a0 + mvfaclo #0,a0,r1 + test_h_gr32 20000 r1 + mvfachi #0,a0,r1 + test_h_gr32 0 r1 + mov #300, r1 + mov #200, r2 + emaca r1,r2,a1 + mvfaclo #0,a1,r1 + test_h_gr32 60000 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + + pass + diff --git a/sim/testsuite/sim/rx/emsba.s b/sim/testsuite/sim/rx/emsba.s new file mode 100644 index 0000000..a20c963 --- /dev/null +++ b/sim/testsuite/sim/rx/emsba.s @@ -0,0 +1,24 @@ +# RX testcase for emsba +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #100, r1 + mov #200, r2 + emsba r1,r2,a0 + mvfaclo #0,a0,r1 + test_h_gr32 -20000 r1 + mvfachi #0,a0,r1 + test_h_gr32 -1 r1 + mov #300, r1 + mov #200, r2 + emsba r1,r2,a1 + mvfaclo #0,a1,r1 + test_h_gr32 -60000 r1 + mvfachi #0,a1,r1 + test_h_gr32 -1 r1 + + pass + diff --git a/sim/testsuite/sim/rx/emul.s b/sim/testsuite/sim/rx/emul.s new file mode 100644 index 0000000..cbbac82 --- /dev/null +++ b/sim/testsuite/sim/rx/emul.s @@ -0,0 +1,92 @@ +# RX testcase for emul +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +emul_imm8: + mov #0xf0000001,r1 + emul #0x10,r1 + test_h_gr32 0x10 r1 + test_h_gr32 0xffffffff r2 +emul_imm16: + emul #1000,r1 + test_h_gr32 16000 r1 + test_h_gr32 0 r2 +emul_imm24: + mov.l #0x10000,r1 + emul #0x10000,r1 + test_h_gr32 0 r1 + test_h_gr32 1 r2 +emul_imm32: + mov.l #0x10,r1 + emul #0x10000000,r1 + test_h_gr32 0 r1 + test_h_gr32 1 r2 +emul_reg: + mov #5, r1 + mov r1,r2 + emul r2,r1 + test_h_gr32 25 r1 + test_h_gr32 0 r2 +emul_mem_ind: + mov.l #val, r2 + emul [r2].l,r1 + test_h_gr32 50 r1 + test_h_gr32 0 r2 +emul_mem_dsp8: + mov.l #val-4, r2 + emul 4[r2].l,r1 + test_h_gr32 100 r1 + test_h_gr32 0 r2 +emul_mem_dsp16: + mov.l #val-0x1000, r2 + emul 0x1000[r2].l,r1 + test_h_gr32 200 r1 + test_h_gr32 0 r2 +emulu_imm8: + mov #0xf0000001,r1 + emulu #0x10,r1 + test_h_gr32 0x10 r1 + test_h_gr32 0xf r2 +emulu_imm16: + emulu #1000,r1 + test_h_gr32 16000 r1 + test_h_gr32 0 r2 +emulu_imm24: + mov.l #0x10000,r1 + emulu #0x10000,r1 + test_h_gr32 0 r1 + test_h_gr32 1 r2 +emulu_imm32: + mov.l #0x10,r1 + emulu #0x10000000,r1 + test_h_gr32 0 r1 + test_h_gr32 1 r2 +emulu_reg: + mov #-5, r1 + mov r1,r2 + emul r2,r1 + test_h_gr32 25 r1 + test_h_gr32 0 r2 +emulu_mem_ind: + mov.l #val, r2 + emulu [r2].l,r1 + test_h_gr32 50 r1 + test_h_gr32 0 r2 +emulu_mem_dsp8: + mov.l #val-4, r2 + emulu 4[r2].l,r1 + test_h_gr32 100 r1 + test_h_gr32 0 r2 +emulu_mem_dsp16: + mov.l #val-0x1000, r2 + emulu 0x1000[r2].l,r1 + test_h_gr32 200 r1 + test_h_gr32 0 r2 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/emula.s b/sim/testsuite/sim/rx/emula.s new file mode 100644 index 0000000..44fbd8a --- /dev/null +++ b/sim/testsuite/sim/rx/emula.s @@ -0,0 +1,24 @@ +# RX testcase for emula +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #100, r1 + mov #200, r2 + emula r1,r2,a0 + mvfaclo #0,a0,r1 + test_h_gr32 20000 r1 + mvfachi #0,a0,r1 + test_h_gr32 0 r1 + mov #300, r1 + mov #200, r2 + emula r1,r2,a1 + mvfaclo #0,a1,r1 + test_h_gr32 60000 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + + pass + diff --git a/sim/testsuite/sim/rx/fadd.s b/sim/testsuite/sim/rx/fadd.s new file mode 100644 index 0000000..430fb38 --- /dev/null +++ b/sim/testsuite/sim/rx/fadd.s @@ -0,0 +1,41 @@ +# RX testcase for fadd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start +fadd_imm: + mov #1.0,r1 + fadd #2.0,r1 + test_h_gr32 3.0 r1 +fadd_reg: + mov.l #4.0,r2 + fadd r2,r1 + test_h_gr32 7.0 r1 +fadd_mem_ind: + mov.l #val, r2 + fadd [r2].l,r1 + test_h_gr32 8.0 r1 +fadd_mem_dsp8: + mov.l #val-4, r2 + fadd 4[r2].l,r1 + test_h_gr32 9.0 r1 +fadd_mem_dsp16: + mov.l #val-0x1000, r2 + fadd 0x1000[r2].l,r1 + test_h_gr32 10.0 r1 + .if cpu == 2 +fadd3_reg: + mov.l #4.0,r2 + mov.l #1.0,r3 + fadd r2,r3,r1 + test_h_gr32 5.0 r1 + .endif + + pass + + .data +val: .float 1.0 + diff --git a/sim/testsuite/sim/rx/fcmp.s b/sim/testsuite/sim/rx/fcmp.s new file mode 100644 index 0000000..db06423 --- /dev/null +++ b/sim/testsuite/sim/rx/fcmp.s @@ -0,0 +1,37 @@ +# RX testcase for fcmp +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +fcmp_imm: + mov #1.0,r1 + fcmp #2.0,r1 + test_zero_clear + test_neg_set +fcmp_reg: + mov.l #4.0,r2 + fcmp r2,r1 + test_zero_clear + test_neg_set +fcmp_mem_ind: + mov.l #val, r2 + fcmp [r2].l,r1 + test_zero_set + test_neg_clear +fcmp_mem_dsp8: + mov.l #val-4, r2 + fcmp 4[r2].l,r1 + test_zero_set + test_neg_clear +fcmp_mem_dsp16: + mov.l #val-0x1000, r2 + fcmp 0x1000[r2].l,r1 + test_zero_set + test_neg_clear + pass + + .data +val: .float 1.0 + diff --git a/sim/testsuite/sim/rx/fdiv.s b/sim/testsuite/sim/rx/fdiv.s new file mode 100644 index 0000000..540a081 --- /dev/null +++ b/sim/testsuite/sim/rx/fdiv.s @@ -0,0 +1,43 @@ +# RX testcase for fdiv +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +fdiv_imm: + mov #100.0,r1 + fdiv #2.0,r1 + test_zero_clear + test_neg_clear + test_h_gr32 50.0 r1 +fdiv_reg: + mov.l #2.0,r2 + fdiv r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 25.0 r1 +fdiv_mem_ind: + mov.l #val, r2 + fdiv [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 12.5 r1 +fdiv_mem_dsp8: + mov.l #val-4, r2 + fdiv 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 6.25 r1 +fdiv_mem_dsp16: + mov.l #val-0x1000, r2 + fdiv 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 3.125 r1 + + pass + + .data +val: .float 2.0 + diff --git a/sim/testsuite/sim/rx/fmul.s b/sim/testsuite/sim/rx/fmul.s new file mode 100644 index 0000000..d79a6d3 --- /dev/null +++ b/sim/testsuite/sim/rx/fmul.s @@ -0,0 +1,51 @@ +# RX testcase for fmul +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start +fmul_imm: + mov #10.0,r1 + fmul #2.0,r1 + test_zero_clear + test_neg_clear + test_h_gr32 20.0 r1 +fmul_reg: + mov.l #2.0,r2 + fmul r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 40.0 r1 +fmul_mem_ind: + mov.l #val, r2 + fmul [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 80.0 r1 +fmul_mem_dsp8: + mov.l #val-4, r2 + fmul 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 160.0 r1 +fmul_mem_dsp16: + mov.l #val-0x1000, r2 + fmul 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 320.0 r1 + .if cpu == 2 +fmul3_reg: + mov.l #4.0,r2 + mov.l #6.0,r3 + fmul r3,r2,r1 + test_h_gr32 24.0 r1 + .endif + + pass + + .data +val: .float 2.0 + diff --git a/sim/testsuite/sim/rx/fsqrt.s b/sim/testsuite/sim/rx/fsqrt.s new file mode 100644 index 0000000..3c1d52d --- /dev/null +++ b/sim/testsuite/sim/rx/fsqrt.s @@ -0,0 +1,23 @@ +# RX testcase for add +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #4.0,r2 + fsqrt r2,r1 + test_h_gr32 2.0 r1 + mov #val,r2 + fsqrt [r2],r1 + test_h_gr32 3.0 r1 + fsqrt 4[r2],r1 + test_h_gr32 4.0 r1 + mov #val - 0x1000 + 8,r2 + fsqrt 0x1000[r2],r1 + test_h_gr32 5.0 r1 + + pass + + .data +val: .float 9,16,25 diff --git a/sim/testsuite/sim/rx/fsub.s b/sim/testsuite/sim/rx/fsub.s new file mode 100644 index 0000000..629a2a0 --- /dev/null +++ b/sim/testsuite/sim/rx/fsub.s @@ -0,0 +1,51 @@ +# RX testcase for fsub +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start +fsub_imm: + mov #10.0,r1 + fsub #2.0,r1 + test_zero_clear + test_neg_clear + test_h_gr32 8.0 r1 +fsub_reg: + mov.l #2.0,r2 + fsub r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 6.0 r1 +fsub_mem_ind: + mov.l #val, r2 + fsub [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 4.0 r1 +fsub_mem_dsp8: + mov.l #val-4, r2 + fsub 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2.0 r1 +fsub_mem_dsp16: + mov.l #val-0x1000, r2 + fsub 0x1000[r2].l,r1 + test_zero_set + test_neg_clear + test_h_gr32 0.0 r1 + .if cpu == 2 +fsub3_reg: + mov.l #4.0,r2 + mov.l #1.0,r3 + fsub r3,r2,r1 + test_h_gr32 3.0 r1 + .endif + + pass + + .data +val: .float 2.0 + diff --git a/sim/testsuite/sim/rx/ftoi.s b/sim/testsuite/sim/rx/ftoi.s new file mode 100644 index 0000000..0d21f19 --- /dev/null +++ b/sim/testsuite/sim/rx/ftoi.s @@ -0,0 +1,37 @@ +# RX testcase for ftoi +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +ftoi_reg: + mov.l #12.34,r2 + ftoi r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 12 r1 +ftoi_mem_ind: + mov.l #val, r2 + ftoi [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 +ftoi_mem_dsp8: + mov.l #val-4, r2 + ftoi 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 +ftoi_mem_dsp16: + mov.l #val-0x1000, r2 + ftoi 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 + + pass + + .data +val: .float 2.345 + diff --git a/sim/testsuite/sim/rx/ftou.s b/sim/testsuite/sim/rx/ftou.s new file mode 100644 index 0000000..434933d --- /dev/null +++ b/sim/testsuite/sim/rx/ftou.s @@ -0,0 +1,37 @@ +# RX testcase for ftou +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start +ftou_reg: + mov.l #2147483648.0,r2 + ftou r2,r1 + test_zero_clear + test_neg_set + test_h_gr32 -2147483648 r1 +ftou_mem_ind: + mov.l #val, r2 + ftou [r2].l,r1 + test_zero_clear + test_neg_set + test_h_gr32 -2147483648 r1 +ftou_mem_dsp8: + mov.l #val-4, r2 + ftou 4[r2].l,r1 + test_zero_clear + test_neg_set + test_h_gr32 -2147483648 r1 +ftou_mem_dsp16: + mov.l #val-0x1000, r2 + ftou 0x1000[r2].l,r1 + test_zero_clear + test_neg_set + test_h_gr32 -2147483648 r1 + + pass + + .data +val: .float 2147483648.0 + diff --git a/sim/testsuite/sim/rx/itof.s b/sim/testsuite/sim/rx/itof.s new file mode 100644 index 0000000..055b42f --- /dev/null +++ b/sim/testsuite/sim/rx/itof.s @@ -0,0 +1,37 @@ +# RX testcase for itof +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +itof_reg: + mov.l #12,r2 + itof r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 12.0 r1 +itof_mem_ind: + mov.l #val, r2 + itof [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2.0 r1 +itof_mem_dsp8: + mov.l #val-4, r2 + itof 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2.0 r1 +itof_mem_dsp16: + mov.l #val-0x1000, r2 + itof 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2.0 r1 + + pass + + .data +val: .long 2 + diff --git a/sim/testsuite/sim/rx/jmp.s b/sim/testsuite/sim/rx/jmp.s new file mode 100644 index 0000000..fe3e3b3 --- /dev/null +++ b/sim/testsuite/sim/rx/jmp.s @@ -0,0 +1,12 @@ +# RX testcase for jmp +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #1f,r1 + jmp r1 + fail +1: + pass diff --git a/sim/testsuite/sim/rx/machilo.s b/sim/testsuite/sim/rx/machilo.s new file mode 100644 index 0000000..2d534ae --- /dev/null +++ b/sim/testsuite/sim/rx/machilo.s @@ -0,0 +1,53 @@ +# RX testcase for add +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + sub r1,r1 + mvtachi r1 + mvtaclo r1 + mov #0x20000,r1 + mov #0x30000,r2 + machi r1,r2 + mvfacmi r1 + test_h_gr32 6 r1 + mvfachi r1 + test_h_gr32 0 r1 + mov #0x3,r1 + mov #0x4,r2 + maclo r1,r2 + mvfacmi r1 + test_h_gr32 0x12 r1 + mvfachi r1 + test_h_gr32 0 r1 + .if cpu == 2 + sub r1,r1 + mvtachi r1,a1 + mvtaclo r1,a1 + mvtacgu r1,a1 + mov #0x20000,r1 + mov #0x30000,r2 + machi r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 6 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + mov #0x3,r1 + mov #0x4,r2 + maclo r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x12 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + mov #0x4,r1 + mov #0x50000,r2 + maclh r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x26 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + .endif + pass diff --git a/sim/testsuite/sim/rx/max.s b/sim/testsuite/sim/rx/max.s new file mode 100644 index 0000000..aa17928 --- /dev/null +++ b/sim/testsuite/sim/rx/max.s @@ -0,0 +1,45 @@ +# RX testcase for max +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +max_imm8: + mov #2,r1 + max #1,r1 + test_h_gr32 2 r1 +max_imm16: + mov #0x8000,r1 + max #0x1000,r1 + test_h_gr32 0x8000 r1 +max_imm24: + mov #0x100000,r1 + max #0x200000,r1 + test_h_gr32 0x200000 r1 +max_imm32: + mov #0x80000000,r1 + max #0x40000000,r1 + test_h_gr32 0x40000000 r1 +max_reg: + mov #0x80000000,r2 + max r2,r1 + test_h_gr32 0x40000000 r1 +max_mem_ind: + mov #10,r1 + mov #val, r2 + max [r2],r1 + test_h_gr32 10 r1 +max_mem_dsp8: + mov #val-4, r2 + max 4[r2],r1 + test_h_gr32 10 r1 +max_mem_dsp16: + mov #val-0x1000, r2 + max 0x1000[r2],r1 + test_h_gr32 10 r1 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/min.s b/sim/testsuite/sim/rx/min.s new file mode 100644 index 0000000..53f97c4 --- /dev/null +++ b/sim/testsuite/sim/rx/min.s @@ -0,0 +1,45 @@ +# RX testcase for min +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +min_imm8: + mov #2,r1 + min #1,r1 + test_h_gr32 1 r1 +min_imm16: + mov #0x8000,r1 + min #0x1000,r1 + test_h_gr32 0x1000 r1 +min_imm24: + mov #0x100000,r1 + min #0x200000,r1 + test_h_gr32 0x100000 r1 +min_imm32: + mov #0x80000000,r1 + min #0x40000000,r1 + test_h_gr32 0x80000000 r1 +min_reg: + mov #0x80000000,r2 + min r2,r1 + test_h_gr32 0x80000000 r1 +min_mem_ind: + mov #2,r1 + mov #val, r2 + min [r2],r1 + test_h_gr32 2 r1 +min_mem_dsp8: + mov #val-4, r2 + min 4[r2],r1 + test_h_gr32 2 r1 +min_mem_dsp16: + mov #val-0x1000, r2 + min 0x1000[r2],r1 + test_h_gr32 2 r1 + + pass + + .data +val: .long 10 diff --git a/sim/testsuite/sim/rx/mov.s b/sim/testsuite/sim/rx/mov.s new file mode 100644 index 0000000..9dd45f4 --- /dev/null +++ b/sim/testsuite/sim/rx/mov.s @@ -0,0 +1,196 @@ +# RX testcase for mov +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + set_gr_a5a5 1 + mov #val,r2 + mov.b r1,[r2] + mov.w r1,2[r2] + mov.l r1,4[r2] + mov.b [r2],r1 + test_h_gr32 0xffffffa5 r1 + mov.w 2[r2],r1 + test_h_gr32 0xffffa5a5 r1 + mov.l 4[r2],r1 + test_h_gr32 0xa5a5a5a5 r1 + mov #1,r1 + test_h_gr32 1 r1 + mov.b #0x01,[r2] + mov.w #0x23,2[r2] + mov.l #0x45,4[r2] + mov.b [r2],r1 + test_h_gr32 0x01 r1 + mov.w 2[r2],r1 + test_h_gr32 0x23 r1 + mov.l 4[r2],r1 + test_h_gr32 0x45 r1 + mov #0x10,r1 + test_h_gr32 0x10 r1 + mov #0x80,r1 + test_h_gr32 0x80 r1 + mov #0x8000,r1 + test_h_gr32 0x8000 r1 + mov #0x800000,r1 + test_h_gr32 0x800000 r1 + mov #0x80000000,r1 + test_h_gr32 0x80000000 r1 + mov #0x80,r1 + mov.b r1,r2 + test_h_gr32 0xffffff80 r2 + mov #0x8000,r1 + mov.w r1,r2 + test_h_gr32 0xffff8000 r2 + mov #0x80000000,r1 + mov.l r1,r2 + test_h_gr32 0x80000000 r2 + mov.l #val,r2 + mov.l #val-4,r3 + mov.l #val-0x1000,r4 + mov.b #0x01,[r2] + mov.b [r2],r1 + test_h_gr32 0x01 r1 + mov.b #0x23,4[r3] + mov.b [r2],r1 + test_h_gr32 0x23 r1 + mov.b #0x45,0x1000[r4] + mov.b [r2],r1 + test_h_gr32 0x45 r1 + mov.w #0x80,[r2] + mov.w [r2],r1 + test_h_gr32 0x80 r1 + mov.w #0x80,4[r3] + mov.w [r2],r1 + test_h_gr32 0x80 r1 + mov.w #0x80,0x1000[r4] + mov.w [r2],r1 + test_h_gr32 0x80 r1 + mov.w #0x1234,[r2] + mov.w [r2],r1 + test_h_gr32 0x1234 r1 + mov.w #0x4567,4[r3] + mov.w [r2],r1 + test_h_gr32 0x4567 r1 + mov.w #0x89ab,0x1000[r4] + mov.w [r2],r1 + test_h_gr32 0xffff89ab r1 + mov.l #0x123456,[r2] + mov.l [r2],r1 + test_h_gr32 0x123456 r1 + mov.l #0x456789,4[r3] + mov.l [r2],r1 + test_h_gr32 0x456789 r1 + mov.l #0x89abcd,0x1000[r4] + mov.l [r2],r1 + test_h_gr32 0x89abcd r1 + mov.l #0x12345678,[r2] + mov.l [r2],r1 + test_h_gr32 0x12345678 r1 + mov.l #0x89abcdef,4[r3] + mov.l [r2],r1 + test_h_gr32 0x89abcdef r1 + mov.l #0x76543210,0x1000[r4] + mov.l [r2],r1 + test_h_gr32 0x876543210 r1 + mov #4,r1 + mov.b r1,[r1,r3] + mov.b [r2],r1 + test_h_gr32 4 r1 + mov #2,r1 + mov.w r1,[r1,r3] + mov.w [r2],r1 + test_h_gr32 2 r1 + mov #0x1000/4,r1 + mov.l r1,[r1,r4] + mov.l [r2],r1 + test_h_gr32 0x1000/4 r1 + mov #val+4,r5 + mov.b #0x12,[r2] + mov.b [r2],[r5] + mov.b [r5],r1 + test_h_gr32 0x12 r1 + mov.w #0x1234,[r2] + mov.w [r2],[r5] + mov.w [r5],r1 + test_h_gr32 0x1234 r1 + mov.l #0x12345678,[r2] + mov.l [r2],[r5] + mov.l [r5],r1 + test_h_gr32 0x12345678 r1 + mov.b #0x12,[r2] + mov.b [r2],8[r3] + mov.b 8[r3],r1 + test_h_gr32 0x12 r1 + mov.w #0x1234,[r2] + mov.w [r2],8[r3] + mov.w 8[r3],r1 + test_h_gr32 0x1234 r1 + mov.l #0x12345678,[r2] + mov.l [r2],8[r3] + mov.l 8[r3],r1 + test_h_gr32 0x12345678 r1 + mov.b #0x12,[r2] + mov.b [r2],0x1004[r4] + mov.b 0x1004[r4],r1 + test_h_gr32 0x12 r1 + mov.w #0x1234,[r2] + mov.w [r2],0x1004[r4] + mov.w 0x1004[r4],r1 + test_h_gr32 0x1234 r1 + mov.l #0x12345678,[r2] + mov.l [r2],0x1004[r4] + mov.l 0x1004[r4],r1 + test_h_gr32 0x12345678 r1 + mov.b #0x12,[r2] + mov.b 4[r3],0x1004[r4] + mov.b 0x1004[r4],r1 + test_h_gr32 0x12 r1 + mov.w #0x1234,[r2] + mov.w 4[r3],0x1004[r4] + mov.w 0x1004[r4],r1 + test_h_gr32 0x1234 r1 + mov.l #0x12345678,[r2] + mov.l 4[r3],0x1004[r4] + mov.l 0x1004[r4],r1 + test_h_gr32 0x12345678 r1 + mov.b #0x12,[r2] + mov.b 0x1000[r4],4[r3] + mov.b 4[r3],r1 + test_h_gr32 0x12 r1 + mov.w #0x1234,[r2] + mov.w 0x1000[r4],4[r3] + mov.w 4[r3],r1 + test_h_gr32 0x1234 r1 + mov.l #0x12345678,[r2] + mov.l 0x1000[r4],4[r3] + mov.l 4[r3],r1 + test_h_gr32 0x12345678 r1 + mov #val+9,r1 + mov #0x12345678,r2 + mov.l r2,[-r1] + mov.w r2,[-r1] + mov.b r2,[-r1] + mov.b [r1+],r2 + test_h_gr32 0x78 r2 + mov.w [r1+],r2 + test_h_gr32 0x5678 r2 + mov.l [r1+],r2 + test_h_gr32 0x12345678 r2 + mov #val,r1 + mov #0x12345678,r2 + mov.l r2,[r1+] + mov.w r2,[r1+] + mov.b r2,[r1+] + mov.b [-r1],r2 + test_h_gr32 0x78 r2 + mov.w [-r1],r2 + test_h_gr32 0x5678 r2 + mov.l [-r1],r2 + test_h_gr32 0x12345678 r2 + + pass + + .data +val: .space 16 diff --git a/sim/testsuite/sim/rx/movlico.s b/sim/testsuite/sim/rx/movlico.s new file mode 100644 index 0000000..3c9c8fe --- /dev/null +++ b/sim/testsuite/sim/rx/movlico.s @@ -0,0 +1,22 @@ +# RX testcase for add +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov.l #0x12345678,r1 + mov.l #val,r2 + movco r1,[r2] + test_h_gr32 1 r1 + movli [r2],r1 + mov #0x5a5a5a5a,r1 + movco r1,[r2] + test_h_gr32 0 r1 + mov.l [r2],r1 + test_h_gr32 0x5a5a5a5a r1 + + pass + + .data +val: .long 0xa5a5a5a5 diff --git a/sim/testsuite/sim/rx/movu.s b/sim/testsuite/sim/rx/movu.s new file mode 100644 index 0000000..5289c94 --- /dev/null +++ b/sim/testsuite/sim/rx/movu.s @@ -0,0 +1,67 @@ +# RX testcase for movu +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + set_gr_a5a5 1 + mov #valb,r2 + movu.b [r2],r1 + test_h_gr32 0x80 r1 + mov #valw,r2 + movu.w [r2],r1 + test_h_gr32 0x8000 r1 + mov #0x8888,r2 + movu.b r2,r1 + test_h_gr32 0x88 r1 + movu.w r2,r1 + test_h_gr32 0x8888 r1 + mov #valb,r2 + movu.b [r2],r10 + test_h_gr32 0x80 r10 + mov #valb-0x40,r2 + movu.b 0x40[r2],r10 + test_h_gr32 0x80 r10 + mov #valb-0x1000,r2 + movu.b 0x1000[r2],r10 + test_h_gr32 0x80 r10 + mov #valb-0x1000,r2 + mov #0x1000,r3 + movu.b [r3,r2],r10 + test_h_gr32 0x80 r10 + mov #valw,r2 + movu.w [r2],r10 + test_h_gr32 0x8000 r10 + mov #valw-0x40,r2 + movu.w 0x40[r2],r10 + test_h_gr32 0x8000 r10 + mov #valw-0x1000,r2 + movu.w 0x1000[r2],r10 + test_h_gr32 0x8000 r10 + mov #valw-0x1000,r2 + mov #0x1000/2,r3 + movu.w [r3,r2],r10 + test_h_gr32 0x8000 r10 + mov #valb,r2 + movu.b [r2+],r1 + test_h_gr32 0x80 r1 + test_h_gr32 valb+1 r2 + mov #valw,r2 + movu.w [r2+],r1 + test_h_gr32 0x8000 r1 + test_h_gr32 valw+2 r2 + mov #valb+1,r2 + movu.b [-r2],r1 + test_h_gr32 0x80 r1 + test_h_gr32 valb r2 + mov #valw+2,r2 + movu.w [-r2],r1 + test_h_gr32 0x8000 r1 + test_h_gr32 valw r2 + + pass + + .data +valw: .word 0x8000 +valb: .byte 0x80 diff --git a/sim/testsuite/sim/rx/msbhilo.s b/sim/testsuite/sim/rx/msbhilo.s new file mode 100644 index 0000000..3a21981 --- /dev/null +++ b/sim/testsuite/sim/rx/msbhilo.s @@ -0,0 +1,43 @@ +# RX testcase for add +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #0x20000,r1 + mov #0x30000,r2 + msbhi r1,r2,a0 + mvfacmi r1 + test_h_gr32 -6 r1 + mvfachi r1 + test_h_gr32 -1 r1 + mov #0x3,r1 + mov #0x4,r2 + msblo r1,r2,a0 + mvfacmi r1 + test_h_gr32 -18 r1 + mvfachi r1 + test_h_gr32 -1 r1 + mov #0x20000,r1 + mov #0x30000,r2 + msbhi r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 -6 r1 + mvfachi #0,a1,r1 + test_h_gr32 -1 r1 + mov #0x3,r1 + mov #0x4,r2 + msblo r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 -18 r1 + mvfachi #0,a1,r1 + test_h_gr32 -1 r1 + mov #0x4,r1 + mov #0x50000,r2 + msblh r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 -38 r1 + mvfachi #0,a1,r1 + test_h_gr32 -1 r1 + pass diff --git a/sim/testsuite/sim/rx/mul.s b/sim/testsuite/sim/rx/mul.s new file mode 100644 index 0000000..979acd7 --- /dev/null +++ b/sim/testsuite/sim/rx/mul.s @@ -0,0 +1,52 @@ +# RX testcase for mul +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +mul_imm4: + mov.l #3,r1 + mul #3,r1 + test_h_gr32 9 r1 +mul_imm8: + mul #20,r1 + test_h_gr32 180 r1 +mul_imm16: + mul #1000,r1 + test_h_gr32 180000 r1 +mul_imm24: + mov.l #3,r1 + mul #0x10000,r1 + test_h_gr32 0x30000 r1 +mul_imm32: + mov.l #3,r1 + mul #0x1000000,r1 + test_h_gr32 0x3000000 r1 +mul_reg: + mov #5, r1 + mov r1,r2 + mul r2,r1 + test_h_gr32 25 r1 +mul_mem_ind: + mov.l #val, r2 + mul [r2].l,r1 + test_h_gr32 50 r1 +mul_mem_dsp8: + mov.l #val-4, r2 + mul 4[r2].l,r1 + test_h_gr32 100 r1 +mul_mem_dsp16: + mov.l #val-0x1000, r2 + mul 0x1000[r2].l,r1 + test_h_gr32 200 r1 +mul3_reg: + mov #6, r1 + mov r1,r2 + mul r1,r2,r3 + test_h_gr32 36 r3 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/mulhilo.s b/sim/testsuite/sim/rx/mulhilo.s new file mode 100644 index 0000000..083d10c --- /dev/null +++ b/sim/testsuite/sim/rx/mulhilo.s @@ -0,0 +1,54 @@ +# RX testcase for add +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + sub r1,r1 + mvtachi r1 + mvtaclo r1 + mov #0x20000,r1 + mov #0x30000,r2 + mulhi r1,r2 + mvfacmi r1 + test_h_gr32 0x6 r1 + mvfachi r1 + test_h_gr32 0 r1 + mov #0x3,r1 + mov #0x4,r2 + mullo r1,r2 + mvfacmi r1 + test_h_gr32 0xc r1 + mvfachi r1 + test_h_gr32 0 r1 + .if cpu == 2 + sub r1,r1 + mvtachi r1,a1 + mvtaclo r1,a1 + mvtacgu r1,a1 + mov #0x20000,r1 + mov #0x30000,r2 + mulhi r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x6 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + mov #0x3,r1 + mov #0x4,r2 + mullo r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0xc r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + mov #0x4,r1 + mov #0x50000,r2 + mullh r1,r2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x14 r1 + mvfachi #0,a1,r1 + test_h_gr32 0 r1 + .endif + + pass diff --git a/sim/testsuite/sim/rx/mvacc.s b/sim/testsuite/sim/rx/mvacc.s new file mode 100644 index 0000000..ac6d3f4 --- /dev/null +++ b/sim/testsuite/sim/rx/mvacc.s @@ -0,0 +1,28 @@ +# RX testcase for add +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #0x12345678,r1 + mvtachi r1 + mvtaclo r1 + mvfacmi r1 + test_h_gr32 0x56781234 r1 + mvfachi r1 + test_h_gr32 0x12345678 r1 + .if cpu == 2 + mvtacgu r1,a0 + mvfacmi #1,a0,r1 + test_h_gr32 0xacf02468 r1 + mvfachi #2,a0,r1 + test_h_gr32 0x48d159e0 r1 + mvfacgu #0,a0,r1 + test_h_gr32 0x78 r1 + mvfaclo #0,a0,r1 + test_h_gr32 0x12345678 r1 + .endif + + pass diff --git a/sim/testsuite/sim/rx/mvftc.s b/sim/testsuite/sim/rx/mvftc.s new file mode 100644 index 0000000..ed98ba8 --- /dev/null +++ b/sim/testsuite/sim/rx/mvftc.s @@ -0,0 +1,36 @@ +# RX testcase for mvfc/mvtc +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #0x1,r1 + mvtc r1,ISP + mov #0x2,r1 + mvtc r1,USP + mov #0x3,r1 + mvtc r1,INTB + mov #0x4,r1 + mvtc r1,BPC + mov #0x5,r1 + mvtc r1,BPSW + mov #0x6,r1 + mvtc r1,FINTV + mvfc ISP,r1 + test_h_gr32 1 r1 + mvfc USP,r1 + test_h_gr32 2 r1 + mvfc INTB,r1 + test_h_gr32 3 r1 + mvfc BPC,r1 + test_h_gr32 4 r1 + mvfc BPSW,r1 + test_h_gr32 5 r1 + mvfc FINTV,r1 + test_h_gr32 6 r1 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/neg.s b/sim/testsuite/sim/rx/neg.s new file mode 100644 index 0000000..7eb6dbf --- /dev/null +++ b/sim/testsuite/sim/rx/neg.s @@ -0,0 +1,17 @@ +# RX testcase for neg +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #1,r1 + neg r1 + test_h_gr32 -1 r1 + neg r1,r2 + test_h_gr32 1 r2 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/not.s b/sim/testsuite/sim/rx/not.s new file mode 100644 index 0000000..f78203a --- /dev/null +++ b/sim/testsuite/sim/rx/not.s @@ -0,0 +1,17 @@ +# RX testcase for not +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #1,r1 + not r1 + test_h_gr32 0xfffffffe r1 + not r1,r2 + test_h_gr32 1 r2 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/or.s b/sim/testsuite/sim/rx/or.s new file mode 100644 index 0000000..1fdd286 --- /dev/null +++ b/sim/testsuite/sim/rx/or.s @@ -0,0 +1,69 @@ +# RX testcase for or +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +or_imm4: + mov #2,r1 + or #1,r1 + test_zero_clear + test_neg_clear + test_h_gr32 3 r1 +or_imm8: + or #0x10,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x13 r1 +or_imm16: + or #0x1000,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x1013 r1 +or_imm24: + or #0x100000,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x101013 r1 +or_imm32: + or #0x10000000,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x10101013 r1 +or_reg: + mov.l #0x20000000,r2 + or r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x30101013 r1 +or_mem_ind: + mov #val, r2 + or [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x3010101b r1 +or_mem_dsp8: + mov #val-4, r2 + or 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x3010101b r1 +or_mem_dsp16: + sub r1,r1 + mov #val-0x1000, r2 + or 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 8 r1 +or3_reg: + mov.l #0x80000000,r2 + or r2,r1,r3 + test_zero_clear + test_neg_set + test_h_gr32 0x80000008 r3 + + pass + + .data +val: .long 8 diff --git a/sim/testsuite/sim/rx/pushpop.s b/sim/testsuite/sim/rx/pushpop.s new file mode 100644 index 0000000..b0d6ce2 --- /dev/null +++ b/sim/testsuite/sim/rx/pushpop.s @@ -0,0 +1,48 @@ +# RX testcase for push/pop +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #1,r1 + push.l r1 + mov #val,r1 + push [r1] + mov #val-4,r1 + push 4[r1] + mov #val-0x1000,r1 + push 0x1000[r1] + pop r4 + pop r3 + pop r2 + pop r1 + test_h_gr32 1 r1 + test_h_gr32 2 r2 + test_h_gr32 2 r3 + test_h_gr32 2 r4 + mov #123456,r1 + mvtc r1,intb + pushc intb + popc intb + mvfc intb,r2 + test_h_gr32 123456 r2 + mov #1,r1 + mov #2,r2 + mov #3,r3 + mov #4,r4 + pushm r1-r4 + sub r1,r1 + sub r2,r2 + sub r3,r3 + sub r4,r4 + popm r1-r4 + test_h_gr32 1 r1 + test_h_gr32 2 r2 + test_h_gr32 3 r3 + test_h_gr32 4 r4 + + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/racw.s b/sim/testsuite/sim/rx/racw.s new file mode 100644 index 0000000..bae6f5a --- /dev/null +++ b/sim/testsuite/sim/rx/racw.s @@ -0,0 +1,38 @@ +# RX testcase for add +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov #0x40000000,r1 + mvtaclo r1 + sub r1,r1 + mvtachi r1 + racw #1 + mvfacmi r1 + test_h_gr32 0x10000 r1 + mvfachi r1 + test_h_gr32 1 r1 + .if cpu == 2 + mov #0x40000000,r1 + mvtaclo r1,a1 + sub r1,r1 + mvtachi r1,a1 + racw #2,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x10000 r1 + mvfachi #0,a1,r1 + test_h_gr32 1 r1 + mov #0x80,r1 + mvtacgu r1,a1 + racl #1,a1 + mvfacmi #0,a1,r1 + test_h_gr32 0x20000 r1 + mvfachi #0,a1,r1 + test_h_gr32 2 r1 + mvfacgu #0,a1,r1 + test_h_gr32 0 r1 + .endif + pass diff --git a/sim/testsuite/sim/rx/rdacw.s b/sim/testsuite/sim/rx/rdacw.s new file mode 100644 index 0000000..66186ed --- /dev/null +++ b/sim/testsuite/sim/rx/rdacw.s @@ -0,0 +1,19 @@ +# RX testcase for rdacw +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + mov.l #-1,r1 + mvtaclo r1,a0 + rdacw #2,a0 + mvfacmi #0,a0,r1 + test_h_gr32 0x30000 r1 + mov.l #-1,r1 + mvtaclo r1,a0 + rdacl #2,a0 + mvfacmi #0,a0,r1 + test_h_gr32 0xf0000 r1 + + pass diff --git a/sim/testsuite/sim/rx/rev.s b/sim/testsuite/sim/rx/rev.s new file mode 100644 index 0000000..120cb58 --- /dev/null +++ b/sim/testsuite/sim/rx/rev.s @@ -0,0 +1,14 @@ +# RX testcase for revl/revw +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #0x12345678,r1 + revl r1,r2 + test_h_gr32 0x78563412 r2 + revw r1,r2 + test_h_gr32 0x34127856 r2 + + pass diff --git a/sim/testsuite/sim/rx/rmpa.s b/sim/testsuite/sim/rx/rmpa.s new file mode 100644 index 0000000..e1b67cb --- /dev/null +++ b/sim/testsuite/sim/rx/rmpa.s @@ -0,0 +1,23 @@ +# RX testcase for rmpa +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + sub r4,r4 + sub r5,r5 + sub r6,r6 + mov #val1,r1 + mov #val2,r2 + mov #10,r3 + rmpa.w + test_h_gr32 110 r4 + test_h_gr32 0 r5 + test_h_gr32 0 r6 + pass + + .data +val1: .word 1,2,3,4,5,6,7,8,9,10 +val2: .word 10,9,8,7,6,5,4,3,2,1 + diff --git a/sim/testsuite/sim/rx/rot.s b/sim/testsuite/sim/rx/rot.s new file mode 100644 index 0000000..38a459f --- /dev/null +++ b/sim/testsuite/sim/rx/rot.s @@ -0,0 +1,46 @@ +# RX testcase for rolc/rorc/rotl/rotr +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + clear_carry_flag + mov.l #0x80000000,r1 + rolc r1 + test_carry_set + test_zero_set + test_neg_clear + test_h_gr32 0 r1 + clear_carry_flag + rorc r1 + test_carry_clear + test_zero_set + test_neg_clear + test_h_gr32 0 r1 + mov.l #0x80000000,r1 + rotl #1,r1 + test_carry_set + test_zero_clear + test_neg_clear + test_h_gr32 1 r1 + mov #1,r2 + rotl r2,r1 + test_carry_clear + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 + rotr #1,r1 + test_carry_clear + test_zero_clear + test_neg_clear + test_h_gr32 1 r1 + rotr r2,r1 + test_carry_set + test_zero_clear + test_neg_set + test_h_gr32 0x80000000 r1 + pass + + .data +val: .long 2 diff --git a/sim/testsuite/sim/rx/round.s b/sim/testsuite/sim/rx/round.s new file mode 100644 index 0000000..cef2e24 --- /dev/null +++ b/sim/testsuite/sim/rx/round.s @@ -0,0 +1,37 @@ +# RX testcase for round +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +round_reg: + mov.l #12.68,r2 + round r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 13 r1 +round_mem_ind: + mov.l #val, r2 + round [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 +round_mem_dsp8: + mov.l #val-4, r2 + round 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 +round_mem_dsp16: + mov.l #val-0x1000, r2 + round 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2 r1 + + pass + + .data +val: .float 2.345 + diff --git a/sim/testsuite/sim/rx/sat.s b/sim/testsuite/sim/rx/sat.s new file mode 100644 index 0000000..3dc38ed --- /dev/null +++ b/sim/testsuite/sim/rx/sat.s @@ -0,0 +1,37 @@ +# RX testcase for fadd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 + + .include "testutils.inc" + + start +sat: sub r1,r1 + sub r4,r4 + sub r5,r5 + sub r6,r6 + clear_overflow_flag + sat r1 + satr + test_h_gr32 0 r1 + test_h_gr32 0 r6 + test_h_gr32 0 r5 + test_h_gr32 0 r4 + + set_overflow_flag + clear_neg_flag + sat r1 + satr + test_h_gr32 0x80000000 r1 + test_h_gr32 0 r6 + test_h_gr32 0x7fffffff r5 + test_h_gr32 0xffffffff r4 + set_overflow_flag + set_neg_flag + sat r1 + satr + test_h_gr32 0x7fffffff r1 + test_h_gr32 0xffffffff r6 + test_h_gr32 0x80000000 r5 + test_h_gr32 0x00000000 r4 + + pass diff --git a/sim/testsuite/sim/rx/sbb.s b/sim/testsuite/sim/rx/sbb.s new file mode 100644 index 0000000..0316508 --- /dev/null +++ b/sim/testsuite/sim/rx/sbb.s @@ -0,0 +1,46 @@ +# RX testcase for sbb +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +sbb_reg: + clear_carry_flag + mov.l #2,r1 + mov.l #1,r2 + sbb r2,r1 + test_zero_set + test_carry_set + test_neg_clear + test_overflow_clear + test_h_gr32 0 r1 +sbb_mem_ind: + mov.l #val, r2 + sbb [r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_overflow_clear + test_h_gr32 -1 r1 +sbb_mem_dsp8: + mov.l #val-4, r2 + sbb 4[r2].l,r1 + test_zero_clear + test_carry_set + test_neg_set + test_overflow_clear + test_h_gr32 -2 r1 +sbb_mem_dsp16: + mov.l #val-0x1000, r2 + sbb 0x1000[r2].l,r1 + test_zero_clear + test_carry_set + test_neg_set + test_overflow_clear + test_h_gr32 -3 r1 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/sccnd.s b/sim/testsuite/sim/rx/sccnd.s new file mode 100644 index 0000000..686e3cb --- /dev/null +++ b/sim/testsuite/sim/rx/sccnd.s @@ -0,0 +1,169 @@ +# RX testcase for SCcnd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #val,r2 + mov #val-4,r3 + mov #val-0x1000,r4 + mov #10,r1 + cmp #5,r1 + scc.b [r2] + scc.b 5[r3] + scc.b 0x1002[r4] + scc.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov.b #0,[r2] + cmp #15,r1 + scnc.b [r2] + scnc.b 5[r3] + scnc.b 0x1002[r4] + scnc.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #-5,r1 + cmp #-10,r1 + scgt.b [r2] + scgt.b 5[r3] + scgt.b 0x1002[r4] + scgt.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #-5,r1 + cmp #-5,r1 + scle.b [r2] + scle.b 5[r3] + scle.b 0x1002[r4] + scle.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #-5,r1 + cmp #-5,r1 + scge.b [r2] + scge.b 5[r3] + scge.b 0x1002[r4] + scge.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #-5,r1 + cmp #-1,r1 + sclt.b [r2] + sclt.b 5[r3] + sclt.b 0x1002[r4] + sclt.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov.l #0xc0000000,r1 + cmp #0x80000000,r1 + scgtu.b [r2] + scgtu.b 5[r3] + scgtu.b 0x1002[r4] + scgtu.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov.l #0xc0000000,r1 + cmp #0xc0000000,r1 + scle.b [r2] + scle.b 5[r3] + scle.b 0x1002[r4] + scle.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #1,r1 + tst r1,r1 + scpz.b [r2] + scpz.b 5[r3] + scpz.b 0x1002[r4] + scpz.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + mov #-1,r1 + tst r1,r1 + scn.b [r2] + scn.b 5[r3] + scn.b 0x1002[r4] + scn.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + set_overflow_flag + sco.b [r2] + sco.b 5[r3] + sco.b 0x1002[r4] + sco.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + clear_overflow_flag + scno.b [r2] + scno.b 5[r3] + scno.b 0x1002[r4] + scno.l r5 + test_h_gr32 1 r5 + mov.b [r2],r5 + test_h_gr32 1 r5 + mov.b 1[r2],r5 + test_h_gr32 1 r5 + mov.b 2[r2],r5 + test_h_gr32 1 r5 + + pass + + .data +val: .space 8 diff --git a/sim/testsuite/sim/rx/scmpu.s b/sim/testsuite/sim/rx/scmpu.s new file mode 100644 index 0000000..01c614e --- /dev/null +++ b/sim/testsuite/sim/rx/scmpu.s @@ -0,0 +1,26 @@ +# RX testcase for scmpu +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #str1,r1 + mov #str1_ok,r2 + mov #128,r3 + scmpu + test_zero_set + test_carry_set + mov #str1,r1 + mov #str1_ng,r2 + mov #128,r3 + scmpu + test_zero_clear + test_carry_set + + pass + + .data +str1: .asciz "abcdefghijklmnopqrstuvwxyz" +str1_ok: .asciz "abcdefghijklmnopqrstuvwxyz" +str1_ng: .asciz "ABCDEFGHIJKLMNOPQRSTUVWXYZ" diff --git a/sim/testsuite/sim/rx/shlr.s b/sim/testsuite/sim/rx/shlr.s new file mode 100644 index 0000000..e329af5 --- /dev/null +++ b/sim/testsuite/sim/rx/shlr.s @@ -0,0 +1,67 @@ +# RX testcase for SCcnd +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #0x80000000,r1 + shar #1,r1 + test_carry_clear + test_zero_clear + test_neg_set + test_overflow_clear + test_h_gr32 0xc0000000 r1 + mov #1,r2 + shar r2,r1 + test_carry_clear + test_zero_clear + test_neg_set + test_overflow_clear + test_h_gr32 0xe0000000 r1 + shar #1,r1,r2 + test_carry_clear + test_zero_clear + test_neg_set + test_overflow_clear + test_h_gr32 0xf0000000 r2 + shll #1,r1 + test_carry_set + test_zero_clear + test_neg_set + test_overflow_clear + test_h_gr32 0xc0000000 r1 + mov #1,r2 + shll r2,r1 + test_carry_set + test_zero_clear + test_neg_set + test_overflow_clear + test_h_gr32 0x80000000 r1 + shll #1,r1,r2 + test_carry_set + test_zero_set + test_neg_clear + test_overflow_set + test_h_gr32 0x00000000 r2 + mov #0xaaaaaaaa,r1 + shlr #1,r1 + test_carry_clear + test_zero_clear + test_neg_clear + test_h_gr32 0x55555555 r1 + mov #1,r2 + shlr r2,r1 + test_carry_set + test_zero_clear + test_neg_clear + test_h_gr32 0x2aaaaaaa r1 + shlr #1,r1,r2 + test_carry_clear + test_zero_clear + test_neg_clear + test_h_gr32 0x15555555 r2 + + pass + + .data diff --git a/sim/testsuite/sim/rx/smovb.s b/sim/testsuite/sim/rx/smovb.s new file mode 100644 index 0000000..26226df --- /dev/null +++ b/sim/testsuite/sim/rx/smovb.s @@ -0,0 +1,53 @@ +# RX testcase for smovb +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #src+127,r2 + mov #dst+127,r1 + mov #128,r3 + smovb + add #1,r1 + add #1,r2 + mov #128,r3 +1: mov.b [r1],r4 + cmp [r2].b,r4 + bne __fail + mov.b #0,[r1] + add #1,r1 + add #1,r2 + sub #1,r3 + bpz 1b + mov #src,r2 + mov #dst,r1 + mov #128,r3 + smovf + mov #128,r3 + mov #src,r2 + mov #dst,r1 +1: mov.b [r1],r4 + cmp [r2].b,r4 + bne __fail + mov.b #0,[r1] + add #1,r1 + add #1,r2 + sub #1,r3 + bpz 1b + + pass +__fail: + fail + exit 1 + + .data +src: + data = 0 + .rept 128 + .byte data + data = data + 1 + .endr +dst: + .space 128 + diff --git a/sim/testsuite/sim/rx/smovu.s b/sim/testsuite/sim/rx/smovu.s new file mode 100644 index 0000000..a715918 --- /dev/null +++ b/sim/testsuite/sim/rx/smovu.s @@ -0,0 +1,23 @@ +# RX testcase for smovu +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #str1,r2 + mov #str1_dst,r1 + mov #128,r3 + smovu + mov #str1,r2 + mov #str1_dst,r1 + mov #128,r3 + scmpu + test_zero_set + + pass + + .data +str1: .asciz "abcdefghijklmnopqrstuvwxyz" +str1_dst: + .space 27 diff --git a/sim/testsuite/sim/rx/sstr.s b/sim/testsuite/sim/rx/sstr.s new file mode 100644 index 0000000..1ef0737 --- /dev/null +++ b/sim/testsuite/sim/rx/sstr.s @@ -0,0 +1,44 @@ +# RX testcase for sstr +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #0x12345678,r2 + mov #dst,r1 + mov #128,r3 + sstr.b + mov #128,r3 + mov #dst,r1 +1: mov.b [r1+],r2 + test_h_gr32 0x78 r2 + sub #1,r3 + bne 1b + mov #0x12345678,r2 + mov #dst,r1 + mov #128/2,r3 + sstr.w + mov #128/2,r3 + mov #dst,r1 +1: mov.w [r1+],r2 + test_h_gr32 0x5678 r2 + sub #1,r3 + bne 1b + mov #0x12345678,r2 + mov #dst,r1 + mov #128/4,r3 + sstr.l + mov #128/4,r3 + mov #dst,r1 +1: mov.l [r1+],r2 + test_h_gr32 0x12345678 r2 + sub #1,r3 + bne 1b + + pass + + .data +dst: + .space 128 + diff --git a/sim/testsuite/sim/rx/stz.s b/sim/testsuite/sim/rx/stz.s new file mode 100644 index 0000000..a808c78 --- /dev/null +++ b/sim/testsuite/sim/rx/stz.s @@ -0,0 +1,52 @@ +# RX testcase for sstr +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names --defsym cpu=1 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start + clear_zero_flag + stnz #1, r1 + stnz #0x100, r2 + stnz #0x10000, r3 + stnz #0x1000000, r4 + stz #2, r1 + stz #0x200, r2 + stz #0x20000, r3 + stz #0x2000000, r4 + test_h_gr32 1 r1 + test_h_gr32 0x100 r2 + test_h_gr32 0x10000 r3 + test_h_gr32 0x1000000 r4 + set_zero_flag + stnz #1, r1 + stnz #0x100, r2 + stnz #0x10000, r3 + stnz #0x1000000, r4 + stz #2, r1 + stz #0x200, r2 + stz #0x20000, r3 + stz #0x2000000, r4 + test_h_gr32 2 r1 + test_h_gr32 0x200 r2 + test_h_gr32 0x20000 r3 + test_h_gr32 0x2000000 r4 + + .if cpu == 2 + mov #1,r1 + mov #2,r2 + clear_zero_flag + stz r2,r1 + test_h_gr32 1 r1 + clear_zero_flag + stnz r2,r1 + test_h_gr32 2 r1 + .endif + + pass + + .data +dst: + .space 128 + diff --git a/sim/testsuite/sim/rx/sub.s b/sim/testsuite/sim/rx/sub.s new file mode 100644 index 0000000..cbc6d18 --- /dev/null +++ b/sim/testsuite/sim/rx/sub.s @@ -0,0 +1,53 @@ +# RX testcase for sub +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +sub_imm4: + mov.l #2,r1 + sub #1,r1 + test_zero_clear + test_carry_set + test_neg_clear + test_h_gr32 1 r1 +sub_reg: + mov.l #1,r2 + sub r2,r1 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r1 +sub_mem_ind: + mov.l #val, r2 + sub [r2].l,r1 + test_zero_clear + test_carry_clear + test_neg_set + test_h_gr32 -1 r1 +sub_mem_dsp8: + mov.l #val-4, r2 + sub 4[r2].l,r1 + test_zero_clear + test_carry_set + test_neg_set + test_h_gr32 -2 r1 +sub_mem_dsp16: + mov.l #val-0x1000, r2 + sub 0x1000[r2].l,r1 + test_zero_clear + test_carry_set + test_neg_set + test_h_gr32 -3 r1 +sub3_reg: + sub r1,r1,r2 + test_zero_set + test_carry_set + test_neg_clear + test_h_gr32 0 r2 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/suntil.s b/sim/testsuite/sim/rx/suntil.s new file mode 100644 index 0000000..79bd268 --- /dev/null +++ b/sim/testsuite/sim/rx/suntil.s @@ -0,0 +1,59 @@ +# RX testcase for suntil +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start + mov #until,r1 + mov #127,r2 + mov #128,r3 + suntil.b + test_zero_set + test_h_gr32 0 r3 + mov #until,r1 + mov #0x7f7e,r2 + mov #128/2,r3 + suntil.w + test_zero_set + test_h_gr32 0 r3 + mov #until,r1 + mov #0x7f7e7d7c,r2 + mov #128/4,r3 + suntil.l + test_zero_set + test_h_gr32 0 r3 + + mov #while,r1 + mov #0,r2 + mov #128,r3 + swhile.b + test_zero_clear + test_h_gr32 3 r3 + mov #while,r1 + mov #0,r2 + mov #128/2,r3 + swhile.w + test_zero_clear + test_h_gr32 1 r3 + mov #while,r1 + mov #0,r2 + mov #128/4,r3 + swhile.l + test_zero_clear + test_h_gr32 0 r3 + + pass + + .data +until: + data = 0 + .rept 128 + .byte data + data = data + 1 + .endr +while: + .rept 31 + .long 0 + .endr + .long 0x01010101 diff --git a/sim/testsuite/sim/rx/testutils.inc b/sim/testsuite/sim/rx/testutils.inc new file mode 100644 index 0000000..06977ae --- /dev/null +++ b/sim/testsuite/sim/rx/testutils.inc @@ -0,0 +1,302 @@ +# Support macros for the Renesas RX assembly test cases. + +; Set up a minimal machine state + .macro start + + .text + .align 2 + .global _start +_start: + bra _main + + .data + .align 2 + .global pass_str + .global fail_str + .global ok_str +pass_str: + .ascii "pass\n" +fail_str: + .ascii "fail\n" +ok_str: + .ascii "ok\n" + + .text + .global _write_and_exit +_write_and_exit: +;ssize_t write(int fd, const void *buf, size_t count); +;Integer arguments have to be zero extended. + mov.l #5,r5 + int #255 + mov.l r4,r1 + bra _exit + + .global _exit +_exit: + mov.l #1,r5 + int #255 + + .global _main +_main: + .endm + + +; Exit with an exit code + .macro exit code + mov.l #\code, r1 + bra _exit + .endm + +; Output "pass\n" + .macro pass + mov.l #0, r1 ; fd == stdout + mov.l #pass_str, r2 ; buf == "pass\n" + mov.l #5, r3 ; len == 5 + sub r4,r4 + bra _write_and_exit + .endm + +; Output "fail\n" + .macro fail + mov.l #0, r1 ; fd == stdout + mov.l #fail_str, r2 ; buf == "fail\n" + mov.l #5, r3 ; len == 5 + mov.l #1,r4 + bra _write_and_exit + .endm + + +; Load an 8-bit immediate value into a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro mvi_h_gr8 val reg + mov.b #\val, \reg + .endm + +; Load a 16-bit immediate value into a general register +; (reg must be r0 - r7) + .macro mvi_h_gr16 val reg + mov.w #\val, \reg + .endm + +; Load a 32-bit immediate value into a general register +; (reg must be er0 - er7) + .macro mvi_h_gr32 val reg + mov.l #\val, \reg + .endm + +; Test the value of an 8-bit immediate against a general register +; (reg must be r0l - r7l or r0h - r7h) + .macro test_h_gr8 val reg + cmp.b #\val, \reg + beq .Ltest_gr8\@ + fail +.Ltest_gr8\@: + .endm + +; Test the value of a 16-bit immediate against a general register +; (reg must be r0 - r7) + .macro test_h_gr16 val reg h=h l=l + cmp.w #\val, \reg + beq .Ltest_gr16\@ + fail +.Ltest_gr16\@: + .endm + +; Test the value of a 32-bit immediate against a general register +; (reg must be er0 - er7) + .macro test_h_gr32 val reg + cmp #\val, \reg + beq .Ltest_gr32\@ + fail +.Ltest_gr32\@: + .endm + +; Set a general register to the fixed pattern 'a5a5a5a5' + .macro set_gr_a5a5 reg + mov.l #0xa5a5a5a5, r\reg + .endm + +; Set all general registers to the fixed pattern 'a5a5a5a5' + .macro set_grs_a5a5 + mov.l #0xa5a5a5a5, r1 + mov.l #0xa5a5a5a5, r2 + mov.l #0xa5a5a5a5, r3 + mov.l #0xa5a5a5a5, r4 + mov.l #0xa5a5a5a5, r5 + mov.l #0xa5a5a5a5, r6 + mov.l #0xa5a5a5a5, r7 + mov.l #0xa5a5a5a5, r8 + mov.l #0xa5a5a5a5, r9 + mov.l #0xa5a5a5a5, r10 + mov.l #0xa5a5a5a5, r11 + mov.l #0xa5a5a5a5, r12 + mov.l #0xa5a5a5a5, r13 + mov.l #0xa5a5a5a5, r14 + mov.l #0xa5a5a5a5, r15 + .endm + +; Test that a general register contains the fixed pattern 'a5a5a5a5' + .macro test_gr_a5a5 reg + test_h_gr32 0xa5a5a5a5 r\reg + .endm + +; Test that all general regs contain the fixed pattern 'a5a5a5a5' + .macro test_grs_a5a5 + test_gr_a5a5 1 + test_gr_a5a5 2 + test_gr_a5a5 3 + test_gr_a5a5 4 + test_gr_a5a5 5 + test_gr_a5a5 6 + test_gr_a5a5 7 + test_gr_a5a5 8 + test_gr_a5a5 9 + test_gr_a5a5 10 + test_gr_a5a5 11 + test_gr_a5a5 12 + test_gr_a5a5 13 + test_gr_a5a5 14 + test_gr_a5a5 15 + .endm + +; Set condition code register to an explicit value + .macro set_ccr val + mvtc #\val, psw + .endm + +; Set all condition code flags to zero + .macro set_ccr_zero + mvtc #0, psw + .endm + +; Set carry flag true + .macro set_carry_flag + setpsw c + .endm + +; Clear carry flag + .macro clear_carry_flag + clrpsw c + .endm + +; Set zero flag true + .macro set_zero_flag + setpsw z + .endm + +; Clear zero flag + .macro clear_zero_flag + clrpsw z + .endm + +; Set sign flag true + .macro set_neg_flag + setpsw s + .endm + +; Clear sign flag + .macro clear_neg_flag + clrpsw s + .endm + +; Set overflow flag true + .macro set_overflow_flag + setpsw o + .endm + +; Clear overflow flag + .macro clear_overflow_flag + clrpsw o + .endm + +; Test that carry flag is clear + .macro test_carry_clear + bnc .Lcc\@ + fail ; carry flag not clear +.Lcc\@: + .endm + +; Test that carry flag is set + .macro test_carry_set + bc .Lcs\@ + fail ; carry flag not clear +.Lcs\@: + .endm + +; Test that overflow flag is clear + .macro test_ovf_clear + bno .Lvc\@ + fail ; overflow flag not clear +.Lvc\@: + .endm + +; Test that overflow flag is set + .macro test_ovf_set + bo .Lvs\@ + fail ; overflow flag not clear +.Lvs\@: + .endm + +; Test that zero flag is clear + .macro test_zero_clear + bne .Lne\@ + fail ; zero flag not clear +.Lne\@: + .endm + +; Test that zero flag is set + .macro test_zero_set + beq .Leq\@ + fail ; zero flag not clear +.Leq\@: + .endm + +; Test that neg flag is clear + .macro test_neg_clear + bpz .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test that neg flag is set + .macro test_neg_set + bn .Lneg\@ + fail ; negative flag not clear +.Lneg\@: + .endm + +; Test that overflow flag is clear + .macro test_overflow_clear + bno .Loverflow\@ + fail ; negative flag not clear +.Loverflow\@: + .endm + +; Test that overflow flag is set + .macro test_overflow_set + bo .Loverflow\@ + fail ; negative flag not clear +.Loverflow\@: + .endm + +; Test ccr against an explicit value + .macro test_ccr val + .text + mov.l r1,[-r0] + mvfc psw, r1 + cmp #\val, r1 + bne .Ltcc\@ + fail +.Ltcc\@: + mov.l [r0+],r1 + .endm + +; Test that all (accessable) condition codes are clear + .macro test_cc_clear + test_carry_clear + test_ovf_clear + test_zero_clear + test_neg_clear + ; leaves H, I, U, and UI untested + .endm + diff --git a/sim/testsuite/sim/rx/tst.s b/sim/testsuite/sim/rx/tst.s new file mode 100644 index 0000000..7736675 --- /dev/null +++ b/sim/testsuite/sim/rx/tst.s @@ -0,0 +1,54 @@ +# RX testcase for tst +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +tst_imm4: + mov.l #2,r1 + tst #2,r1 + test_zero_clear + test_neg_clear +tst_imm8: + tst #0x13,r1 + test_zero_clear + test_neg_clear +tst_imm16: + tst #0xffff,r1 + test_zero_clear + test_neg_clear +tst_imm24: + tst #0xffffff,r1 + test_zero_clear + test_neg_clear +tst_imm32: + mov.l #0x80000000,r1 + tst #0xffffffff,r1 + test_zero_clear + test_neg_set +tst_reg: + mov.l #0x80000000,r2 + tst r2,r1 + test_zero_clear + test_neg_set +tst_mem_ind: + mov.l #val, r2 + tst [r2].l,r1 + test_zero_set + test_neg_clear +tst_mem_dsp8: + mov.l #val-4, r2 + tst 4[r2].l,r1 + test_zero_set + test_neg_clear +tst_mem_dsp16: + mov.l #val-0x1000, r2 + tst 0x1000[r2].l,r1 + test_zero_set + test_neg_clear + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/utof.s b/sim/testsuite/sim/rx/utof.s new file mode 100644 index 0000000..2dee2bf --- /dev/null +++ b/sim/testsuite/sim/rx/utof.s @@ -0,0 +1,37 @@ +# RX testcase for utof +# mach: rxv2 +# as(rxv2): --muse-conventional-section-names --defsym cpu=2 --mcpu=rxv2 + + .include "testutils.inc" + + start +utof_reg: + mov.l #2147483648,r2 + utof r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2147483648.0 r1 +utof_mem_ind: + mov.l #val, r2 + utof [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2147483648.0 r1 +utof_mem_dsp8: + mov.l #val-4, r2 + utof 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2147483648.0 r1 +utof_mem_dsp16: + mov.l #val-0x1000, r2 + utof 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 2147483648.0 r1 + + pass + + .data +val: .long 2147483648 + diff --git a/sim/testsuite/sim/rx/xchg.s b/sim/testsuite/sim/rx/xchg.s new file mode 100644 index 0000000..b1098be --- /dev/null +++ b/sim/testsuite/sim/rx/xchg.s @@ -0,0 +1,36 @@ +# RX testcase for xchg +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +xchg_reg: + mov.l #1,r1 + mov.l #2,r2 + xchg r2,r1 + test_h_gr32 1 r2 + test_h_gr32 2 r1 +xchg_mem_ind: + mov.l #val, r2 + xchg [r2].l,r1 + mov.l [r2],r3 + test_h_gr32 1 r1 + test_h_gr32 2 r3 +tst_mem_dsp8: + mov.l #val-4, r2 + xchg 4[r2].l,r1 + mov.l 4[r2],r3 + test_h_gr32 2 r1 + test_h_gr32 1 r3 +tst_mem_dsp16: + mov.l #val-0x1000, r2 + xchg 0x1000[r2].l,r1 + mov.l 0x1000[r2],r3 + test_h_gr32 1 r1 + test_h_gr32 2 r3 + + pass + + .data +val: .long 1 diff --git a/sim/testsuite/sim/rx/xor.s b/sim/testsuite/sim/rx/xor.s new file mode 100644 index 0000000..0e22199 --- /dev/null +++ b/sim/testsuite/sim/rx/xor.s @@ -0,0 +1,58 @@ +# RX testcase for xor +# mach: rx rxv2 +# as(rx): --muse-conventional-section-names + + .include "testutils.inc" + + start +xor_imm8: + sub r1,r1 + xor #0x10,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x10 r1 +xor_imm16: + xor #0x1010,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x1000 r1 +xor_imm24: + xor #0x101000,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x100000 r1 +xor_imm32: + xor #0x10100000,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x10000000 r1 +xor_reg: + mov.l #0x20000000,r2 + xor r2,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x30000000 r1 +xor_mem_ind: + mov #val, r2 + xor [r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x30000008 r1 +xor_mem_dsp8: + mov #val-4, r2 + xor 4[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 0x30000000 r1 +xor_mem_dsp16: + sub r1,r1 + mov #val-0x1000, r2 + xor 0x1000[r2].l,r1 + test_zero_clear + test_neg_clear + test_h_gr32 8 r1 + + pass + + .data +val: .long 8