From patchwork Tue Dec 8 14:07:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Antoine Tremblay X-Patchwork-Id: 9932 Received: (qmail 38069 invoked by alias); 8 Dec 2015 14:07:34 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 38001 invoked by uid 89); 8 Dec 2015 14:07:34 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_LAZY_DOMAIN_SECURITY autolearn=no version=3.3.2 X-HELO: usplmg21.ericsson.net Received: from usplmg21.ericsson.net (HELO usplmg21.ericsson.net) (198.24.6.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Tue, 08 Dec 2015 14:07:32 +0000 Received: from EUSAAHC001.ericsson.se (Unknown_Domain [147.117.188.75]) by usplmg21.ericsson.net (Symantec Mail Security) with SMTP id A0.48.32102.D14E6665; Tue, 8 Dec 2015 15:07:25 +0100 (CET) Received: from elxa4wqvvz1.dyn.mo.ca.am.ericsson.se (147.117.188.8) by smtps-am.internal.ericsson.com (147.117.188.75) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 8 Dec 2015 09:07:29 -0500 From: Antoine Tremblay To: CC: Antoine Tremblay Subject: [PATCH v7 2/8] Share some ARM target dependent code from GDB with GDBServer. Date: Tue, 8 Dec 2015 09:07:15 -0500 Message-ID: <1449583641-18156-3-git-send-email-antoine.tremblay@ericsson.com> In-Reply-To: <1449583641-18156-1-git-send-email-antoine.tremblay@ericsson.com> References: <1449583641-18156-1-git-send-email-antoine.tremblay@ericsson.com> MIME-Version: 1.0 X-IsSubscribed: yes This patch is in preparation for software single stepping support on ARM it shares some functions and definitions that will be needed. No regressions, tested on ubuntu 14.04 ARMv7 and x86. With gdbserver-{native,extended} / { -marm -mthumb } Not tested: wince/bsd build. gdb/ChangeLog: * arch/arm.c (bitcount): Move from arm-tdep.c. (condition_true): Likewise. * arch/arm.h (Instruction Definitions): Move form arm-tdep.h. (condition_true): Move defenition from arm-tdep.h. (bitcount): Likewise. * arm-tdep.c (condition_true): Move to arch/arm.c. (bitcount): Likewise. * arm-tdep.h (Instruction Definitions): Move to arch/arm.h. * arm-wince-tdep.c: Include arch/arm.h. * armnbsd-tdep.c: Likewise. --- gdb/arch/arm.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++-- gdb/arch/arm.h | 36 +++++++++++++++++++++++++++++++ gdb/arm-tdep.c | 55 ----------------------------------------------- gdb/arm-tdep.h | 29 ------------------------- gdb/arm-wince-tdep.c | 1 + gdb/armnbsd-tdep.c | 1 + 6 files changed, 96 insertions(+), 86 deletions(-) diff --git a/gdb/arch/arm.c b/gdb/arch/arm.c index b11c684..426377f 100644 --- a/gdb/arch/arm.c +++ b/gdb/arch/arm.c @@ -20,8 +20,7 @@ #include "common-defs.h" #include "arm.h" -/* Return the size in bytes of the complete Thumb instruction whose - first halfword is INST1. */ +/* See arm.h. */ int thumb_insn_size (unsigned short inst1) @@ -31,3 +30,60 @@ thumb_insn_size (unsigned short inst1) else return 2; } + +/* See arm.h. */ + +int +bitcount (unsigned long val) +{ + int nbits; + for (nbits = 0; val != 0; nbits++) + val &= val - 1; /* Delete rightmost 1-bit in val. */ + return nbits; +} + +/* See arm.h. */ + +int +condition_true (unsigned long cond, unsigned long status_reg) +{ + if (cond == INST_AL || cond == INST_NV) + return 1; + + switch (cond) + { + case INST_EQ: + return ((status_reg & FLAG_Z) != 0); + case INST_NE: + return ((status_reg & FLAG_Z) == 0); + case INST_CS: + return ((status_reg & FLAG_C) != 0); + case INST_CC: + return ((status_reg & FLAG_C) == 0); + case INST_MI: + return ((status_reg & FLAG_N) != 0); + case INST_PL: + return ((status_reg & FLAG_N) == 0); + case INST_VS: + return ((status_reg & FLAG_V) != 0); + case INST_VC: + return ((status_reg & FLAG_V) == 0); + case INST_HI: + return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); + case INST_LS: + return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); + case INST_GE: + return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); + case INST_LT: + return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); + case INST_GT: + return (((status_reg & FLAG_Z) == 0) + && (((status_reg & FLAG_N) == 0) + == ((status_reg & FLAG_V) == 0))); + case INST_LE: + return (((status_reg & FLAG_Z) != 0) + || (((status_reg & FLAG_N) == 0) + != ((status_reg & FLAG_V) == 0))); + } + return 1; +} diff --git a/gdb/arch/arm.h b/gdb/arch/arm.h index a054776..1a877bc 100644 --- a/gdb/arch/arm.h +++ b/gdb/arch/arm.h @@ -58,6 +58,36 @@ enum gdb_regnum { ARM_LAST_FP_ARG_REGNUM = ARM_F3_REGNUM }; +/* Instruction condition field values. */ +#define INST_EQ 0x0 +#define INST_NE 0x1 +#define INST_CS 0x2 +#define INST_CC 0x3 +#define INST_MI 0x4 +#define INST_PL 0x5 +#define INST_VS 0x6 +#define INST_VC 0x7 +#define INST_HI 0x8 +#define INST_LS 0x9 +#define INST_GE 0xa +#define INST_LT 0xb +#define INST_GT 0xc +#define INST_LE 0xd +#define INST_AL 0xe +#define INST_NV 0xf + +#define FLAG_N 0x80000000 +#define FLAG_Z 0x40000000 +#define FLAG_C 0x20000000 +#define FLAG_V 0x10000000 + +#define CPSR_T 0x20 + +#define XPSR_T 0x01000000 + +/* Size of integer registers. */ +#define INT_REGISTER_SIZE 4 + /* Addresses for calling Thumb functions have the bit 0 set. Here are some macros to test, set, or clear bit 0 of addresses. */ #define IS_THUMB_ADDR(addr) ((addr) & 1) @@ -68,4 +98,10 @@ enum gdb_regnum { first halfword is INST1. */ int thumb_insn_size (unsigned short inst1); +/* Returns true if the condition evaluates to true. */ +int condition_true (unsigned long cond, unsigned long status_reg); + +/* Return number of 1-bits in VAL. */ +int bitcount (unsigned long val); + #endif diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 6ce6f09c..848af97 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -4301,50 +4301,6 @@ convert_to_extended (const struct floatformat *fmt, void *dbl, const void *ptr, &d, dbl); } -static int -condition_true (unsigned long cond, unsigned long status_reg) -{ - if (cond == INST_AL || cond == INST_NV) - return 1; - - switch (cond) - { - case INST_EQ: - return ((status_reg & FLAG_Z) != 0); - case INST_NE: - return ((status_reg & FLAG_Z) == 0); - case INST_CS: - return ((status_reg & FLAG_C) != 0); - case INST_CC: - return ((status_reg & FLAG_C) == 0); - case INST_MI: - return ((status_reg & FLAG_N) != 0); - case INST_PL: - return ((status_reg & FLAG_N) == 0); - case INST_VS: - return ((status_reg & FLAG_V) != 0); - case INST_VC: - return ((status_reg & FLAG_V) == 0); - case INST_HI: - return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); - case INST_LS: - return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); - case INST_GE: - return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); - case INST_LT: - return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); - case INST_GT: - return (((status_reg & FLAG_Z) == 0) - && (((status_reg & FLAG_N) == 0) - == ((status_reg & FLAG_V) == 0))); - case INST_LE: - return (((status_reg & FLAG_Z) != 0) - || (((status_reg & FLAG_N) == 0) - != ((status_reg & FLAG_V) == 0))); - } - return 1; -} - static unsigned long shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, unsigned long pc_val, unsigned long status_reg) @@ -4395,17 +4351,6 @@ shifted_reg_val (struct frame_info *frame, unsigned long inst, int carry, return res & 0xffffffff; } -/* Return number of 1-bits in VAL. */ - -static int -bitcount (unsigned long val) -{ - int nbits; - for (nbits = 0; val != 0; nbits++) - val &= val - 1; /* Delete rightmost 1-bit in val. */ - return nbits; -} - static int thumb_advance_itstate (unsigned int itstate) { diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 3e06f79..9b8447b 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -26,9 +26,6 @@ struct address_space; #include "arch/arm.h" -/* Size of integer registers. */ -#define INT_REGISTER_SIZE 4 - /* Say how long FP registers are. Used for documentation purposes and code readability in this header. IEEE extended doubles are 80 bits. DWORD aligned they use 96 bits. */ @@ -50,32 +47,6 @@ struct address_space; #define NUM_GREGS 16 /* Number of general purpose registers. */ -/* Instruction condition field values. */ -#define INST_EQ 0x0 -#define INST_NE 0x1 -#define INST_CS 0x2 -#define INST_CC 0x3 -#define INST_MI 0x4 -#define INST_PL 0x5 -#define INST_VS 0x6 -#define INST_VC 0x7 -#define INST_HI 0x8 -#define INST_LS 0x9 -#define INST_GE 0xa -#define INST_LT 0xb -#define INST_GT 0xc -#define INST_LE 0xd -#define INST_AL 0xe -#define INST_NV 0xf - -#define FLAG_N 0x80000000 -#define FLAG_Z 0x40000000 -#define FLAG_C 0x20000000 -#define FLAG_V 0x10000000 - -#define CPSR_T 0x20 - -#define XPSR_T 0x01000000 /* Type of floating-point code in use by inferior. There are really 3 models that are traditionally supported (plus the endianness issue), but gcc can diff --git a/gdb/arm-wince-tdep.c b/gdb/arm-wince-tdep.c index 72295ba..3abd89d 100644 --- a/gdb/arm-wince-tdep.c +++ b/gdb/arm-wince-tdep.c @@ -24,6 +24,7 @@ #include "target.h" #include "frame.h" +#include "arch/arm.h" #include "arm-tdep.h" #include "windows-tdep.h" diff --git a/gdb/armnbsd-tdep.c b/gdb/armnbsd-tdep.c index 4c128c2..14eceaa 100644 --- a/gdb/armnbsd-tdep.c +++ b/gdb/armnbsd-tdep.c @@ -20,6 +20,7 @@ #include "defs.h" #include "osabi.h" +#include "arch/arm.h" #include "arm-tdep.h" #include "solib-svr4.h"