[3/6] sim: cr16: push down sd/cpu vars [committed]

Message ID	1447643682-3812-3-git-send-email-vapier@gentoo.org
State	Committed
Delegated to:	Mike Frysinger
Headers	Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk Sender: gdb-patches-owner@sourceware.org From: Mike Frysinger <vapier@gentoo.org> To: gdb-patches@sourceware.org Subject: [PATCH 3/6] sim: cr16: push down sd/cpu vars [committed] Date: Sun, 15 Nov 2015 22:14:39 -0500 Message-Id: <1447643682-3812-3-git-send-email-vapier@gentoo.org> In-Reply-To: <1447643682-3812-1-git-send-email-vapier@gentoo.org> References: <1447643682-3812-1-git-send-email-vapier@gentoo.org>

diff --git a/sim/cr16/ChangeLog b/sim/cr16/ChangeLog index aaf44eb..00169ee 100644 --- a/sim/cr16/ChangeLog +++ b/sim/cr16/ChangeLog @@ -1,5 +1,30 @@ 2015-11-15 Mike Frysinger <vapier@gentoo.org> + * cr16_sim.h (struct simops): Add SIM_DESC and SIM_CPU to func args. + (SET_CREG, SET_HW_CREG, SET_PSR_BIT): Pass sd and cpu to move_to_cr. + (dmem_addr, imem_addr, move_to_cr): Add SIM_DESC and SIM_CPU args. + (RB, SW, RW, SLW, RLW): Pass sd and cpu to dmem_addr. + * endian.c: Change cr16_sim.h include to sim-main.h. + * gencode.c: Likewise. Add SIM_DESC and SIM_CPU args to all OPs. + * interp.c (lookup_hash, map_memory, do_run, dmap_register, + imap_register, sim_cr16_translate_dmap_addr, xfer_mem, + sim_cr16_translate_imap_addr, sim_cr16_translate_addr): Add + SIM_DESC and SIM_CPU args and adjust all callers. + (trace_sd): Delete. + (sim_open): Do not assign trace_sd. + (sim_resume, sim_create_inferior): Set up cpu from the first one + in sd. + (cr16_reg_store): Get sim state from cpu. + * simops.c (move_to_cr): Add SIM_DESC and SIM_CPU args. + (trace_input_func, trace_input, do_trace_output_finish, + do_trace_output_finish, trace_output_40, trace_output_32, + trace_output_16, trace_output_void, trace_output_flag): Add + SIM_DESC arg. + (trace_input_func): Likewise. Change trace_sd to sd. + (OP_*): Add SIM_DESC and SIM_CPU args to all OP funcs. + +2015-11-15 Mike Frysinger <vapier@gentoo.org> + * cr16_sim.h (get_longlong, write_longlong, WRITE_16, READ_64, WRITE_64): Delete. * endian.c (get_longlong, write_longlong): Likewise. diff --git a/sim/cr16/cr16_sim.h b/sim/cr16/cr16_sim.h index e9769ac..5167ade 100644 --- a/sim/cr16/cr16_sim.h +++ b/sim/cr16/cr16_sim.h @@ -66,7 +66,7 @@ struct simops uint32 opcode; int format; char fname[12]; - void (*func)(); + void (*func)(SIM_DESC, SIM_CPU *); int numops; operand_desc operands[4]; }; @@ -251,8 +251,8 @@ struct _state creg_t cregs[16]; /* control registers */ #define CREG(N) (State.cregs[(N)] + 0) -#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 0) -#define SET_HW_CREG(N,VAL) move_to_cr ((N), 0, (VAL), 1) +#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0) +#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1) reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */ #define HELD_SP(N) (State.sp[(N)] + 0) @@ -318,7 +318,7 @@ enum #define PSR CREG (PSR_CR) #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL)) #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL)) -#define SET_PSR_BIT(MASK,VAL) move_to_cr (PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1) +#define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1) #define PSR_SM ((PSR & PSR_SM_BIT) != 0) #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL)) @@ -421,11 +421,11 @@ enum /* sign-extend a 32-bit number */ #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000) -extern uint8 *dmem_addr (uint32 offset); -extern uint8 *imem_addr (uint32); +extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint32 offset); +extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32); extern bfd_vma decode_pc (void); -#define RB(x) (*(dmem_addr(x))) +#define RB(x) (*(dmem_addr (sd, cpu, x))) #define SB(addr,data) ( RB(addr) = (data & 0xff)) #if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE) @@ -440,10 +440,10 @@ extern void write_word (uint8 *addr, uint16 data); extern void write_longword (uint8 *addr, uint32 data); #endif -#define SW(addr,data) write_word(dmem_addr(addr),data) -#define RW(x) get_word(dmem_addr(x)) -#define SLW(addr,data) write_longword(dmem_addr(addr),data) -#define RLW(x) get_longword(dmem_addr(x)) +#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data) +#define RW(x) get_word (dmem_addr (sd, cpu, x)) +#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data) +#define RLW(x) get_longword (dmem_addr (sd, cpu, x)) #define READ_16(x) get_word(x) #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0) @@ -467,7 +467,7 @@ extern void write_longword (uint8 *addr, uint32 data); (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for PSR is masked for zero bits. */ -extern creg_t move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p); +extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p); #ifndef SIGTRAP #define SIGTRAP 5 diff --git a/sim/cr16/endian.c b/sim/cr16/endian.c index 03f79ac..de8c874 100644 --- a/sim/cr16/endian.c +++ b/sim/cr16/endian.c @@ -23,7 +23,7 @@ #ifndef ENDIAN_INLINE #define NO_ENDIAN_INLINE -#include "cr16_sim.h" +#include "sim-main.h" #define ENDIAN_INLINE #endif diff --git a/sim/cr16/gencode.c b/sim/cr16/gencode.c index 3065ebf..6d56908 100644 --- a/sim/cr16/gencode.c +++ b/sim/cr16/gencode.c @@ -53,8 +53,9 @@ write_header (void) /* Loop over instruction table until a full match is found. */ for ( ; i < NUMOPCODES; i++) - printf("void OP_%lX_%X (void);\t\t/* %s */\n", cr16_instruction[i].match, - (32 - cr16_instruction[i].match_bits), cr16_instruction[i].mnemonic); + printf("void OP_%lX_%X (SIM_DESC, SIM_CPU *);\t\t/* %s */\n", + cr16_instruction[i].match, (32 - cr16_instruction[i].match_bits), + cr16_instruction[i].mnemonic); } @@ -66,15 +67,16 @@ write_template (void) { int i = 0,j, k, flags; - printf ("#include \"cr16_sim.h\"\n"); + printf ("#include \"sim-main.h\"\n"); printf ("#include \"simops.h\"\n\n"); for ( ; i < NUMOPCODES; i++) { if (cr16_instruction[i].size != 0) { - printf("/* %s */\nvoid\nOP_%lX_%X ()\n{\n", cr16_instruction[i].mnemonic, - cr16_instruction[i].match, (32 - cr16_instruction[i].match_bits)); + printf ("/* %s */\nvoid\nOP_%lX_%X (SIM_DESC sd, SIM_CPU *cpu)\n{\n", + cr16_instruction[i].mnemonic, cr16_instruction[i].match, + (32 - cr16_instruction[i].match_bits)); /* count operands. */ j = 0; @@ -129,7 +131,7 @@ write_opcodes (void) int i = 0, j = 0, k; /* write out opcode table. */ - printf ("#include \"cr16_sim.h\"\n"); + printf ("#include \"sim-main.h\"\n"); printf ("#include \"simops.h\"\n\n"); printf ("struct simops Simops[] = {\n"); diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c index 981cff4..7f5e044 100644 --- a/sim/cr16/interp.c +++ b/sim/cr16/interp.c @@ -40,9 +40,9 @@ host_callback *cr16_callback; uint32 OP[4]; uint32 sign_flag; -static struct hash_entry *lookup_hash (uint64 ins, int size); +static struct hash_entry *lookup_hash (SIM_DESC, SIM_CPU *, uint64 ins, int size); static void get_operands (operand_desc *s, uint64 mcode, int isize, int nops); -static INLINE uint8 *map_memory (unsigned phys_addr); +static INLINE uint8 *map_memory (SIM_DESC, SIM_CPU *, unsigned phys_addr); #define MAX_HASH 16 @@ -73,7 +73,7 @@ hash(unsigned long long insn, int format) INLINE static struct hash_entry * -lookup_hash (uint64 ins, int size) +lookup_hash (SIM_DESC sd, SIM_CPU *cpu, uint64 ins, int size) { uint32 mask; struct hash_entry *h; @@ -329,7 +329,7 @@ get_operands (operand_desc *s, uint64 ins, int isize, int nops) } static int -do_run (SIM_DESC sd, uint64 mcode) +do_run (SIM_DESC sd, SIM_CPU *cpu, uint64 mcode) { host_callback *cr16_callback = STATE_CALLBACK (sd); struct simops *s= Simops; @@ -340,15 +340,15 @@ do_run (SIM_DESC sd, uint64 mcode) if ((cr16_debug & DEBUG_INSTRUCTION) != 0) (*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode); #endif - - h = lookup_hash(mcode, 1); + + h = lookup_hash (sd, cpu, mcode, 1); if ((h == NULL) || (h->opcode == 0)) return 0; if (h->size == 3) { - iaddr = imem_addr ((uint32)PC + 2); + iaddr = imem_addr (sd, cpu, (uint32)PC + 2); mcode = (mcode << 16) | get_longword( iaddr ); } @@ -365,7 +365,7 @@ do_run (SIM_DESC sd, uint64 mcode) //State.ins_type = h->flags; - (h->ops->func)(); + (h->ops->func) (sd, cpu); return h->size; } @@ -408,17 +408,17 @@ enum }; static unsigned long -dmap_register (void *regcache, int reg_nr) +dmap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) { - uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA + uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA + DMAP0_OFFSET + 2 * reg_nr); return READ_16 (raw); } static unsigned long -imap_register (void *regcache, int reg_nr) +imap_register (SIM_DESC sd, SIM_CPU *cpu, void *regcache, int reg_nr) { - uint8 *raw = map_memory (SIM_CR16_MEMORY_DATA + uint8 *raw = map_memory (sd, cpu, SIM_CR16_MEMORY_DATA + IMAP0_OFFSET + 2 * reg_nr); return READ_16 (raw); } @@ -427,11 +427,15 @@ imap_register (void *regcache, int reg_nr) into a physical address. */ static unsigned long -sim_cr16_translate_dmap_addr (unsigned long offset, +sim_cr16_translate_dmap_addr (SIM_DESC sd, + SIM_CPU *cpu, + unsigned long offset, int nr_bytes, unsigned long *phys, void *regcache, - unsigned long (*dmap_register) (void *regcache, + unsigned long (*dmap_register) (SIM_DESC, + SIM_CPU *, + void *regcache, int reg_nr)) { short map; @@ -451,7 +455,7 @@ sim_cr16_translate_dmap_addr (unsigned long offset, /* Don't cross a BLOCK boundary */ nr_bytes = DMAP_BLOCK_SIZE - (offset % DMAP_BLOCK_SIZE); } - map = dmap_register (regcache, regno); + map = dmap_register (sd, cpu, regcache, regno); if (regno == 3) { /* Always maps to data memory */ @@ -490,11 +494,15 @@ sim_cr16_translate_dmap_addr (unsigned long offset, into a physical address. */ static unsigned long -sim_cr16_translate_imap_addr (unsigned long offset, +sim_cr16_translate_imap_addr (SIM_DESC sd, + SIM_CPU *cpu, + unsigned long offset, int nr_bytes, unsigned long *phys, void *regcache, - unsigned long (*imap_register) (void *regcache, + unsigned long (*imap_register) (SIM_DESC, + SIM_CPU *, + void *regcache, int reg_nr)) { short map; @@ -514,7 +522,7 @@ sim_cr16_translate_imap_addr (unsigned long offset, /* Don't cross a BLOCK boundary */ nr_bytes = IMAP_BLOCK_SIZE - offset; } - map = imap_register (regcache, regno); + map = imap_register (sd, cpu, regcache, regno); sp = (map & 0x3000) >> 12; segno = (map & 0x007f); switch (sp) @@ -543,12 +551,20 @@ sim_cr16_translate_imap_addr (unsigned long offset, } static unsigned long -sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes, - unsigned long *targ_addr, void *regcache, - unsigned long (*dmap_register) (void *regcache, - int reg_nr), - unsigned long (*imap_register) (void *regcache, - int reg_nr)) +sim_cr16_translate_addr (SIM_DESC sd, + SIM_CPU *cpu, + unsigned long memaddr, + int nr_bytes, + unsigned long *targ_addr, + void *regcache, + unsigned long (*dmap_register) (SIM_DESC, + SIM_CPU *, + void *regcache, + int reg_nr), + unsigned long (*imap_register) (SIM_DESC, + SIM_CPU *, + void *regcache, + int reg_nr)) { unsigned long phys; unsigned long seg; @@ -587,13 +603,13 @@ sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes, break; case 0x10: /* in logical data address segment */ - nr_bytes = sim_cr16_translate_dmap_addr (off, nr_bytes, &phys, regcache, - dmap_register); + nr_bytes = sim_cr16_translate_dmap_addr (sd, cpu, off, nr_bytes, &phys, + regcache, dmap_register); break; case 0x11: /* in logical instruction address segment */ - nr_bytes = sim_cr16_translate_imap_addr (off, nr_bytes, &phys, regcache, - imap_register); + nr_bytes = sim_cr16_translate_imap_addr (sd, cpu, off, nr_bytes, &phys, + regcache, imap_register); break; default: @@ -609,7 +625,7 @@ sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes, isn't going to cross a segment boundary. */ uint8 * -map_memory (unsigned phys_addr) +map_memory (SIM_DESC sd, SIM_CPU *cpu, unsigned phys_addr) { uint8 **memory; uint8 *raw; @@ -690,12 +706,12 @@ xfer_mem (SIM_DESC sd, SIM_ADDR virt, uint8 *memory; unsigned long phys; int phys_size; - phys_size = sim_cr16_translate_addr (virt, size, &phys, NULL, + phys_size = sim_cr16_translate_addr (sd, NULL, virt, size, &phys, NULL, dmap_register, imap_register); if (phys_size == 0) return 0; - memory = map_memory (phys); + memory = map_memory (sd, NULL, phys); #ifdef DEBUG if ((cr16_debug & DEBUG_INSTRUCTION) != 0) @@ -746,6 +762,7 @@ cr16_pc_get (sim_cpu *cpu) static void cr16_pc_set (sim_cpu *cpu, sim_cia pc) { + SIM_DESC sd = CPU_STATE (cpu); SET_PC (pc); } @@ -761,8 +778,6 @@ free_state (SIM_DESC sd) static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int); static int cr16_reg_store (SIM_CPU *, int, unsigned char *, int); -SIM_DESC trace_sd = NULL; - SIM_DESC sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, char **argv) { @@ -833,7 +848,6 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, CPU_PC_STORE (cpu) = cr16_pc_set; } - trace_sd = sd; cr16_callback = cb; /* put all the opcodes in the hash table. */ @@ -950,7 +964,7 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, struct bfd *abfd, } uint8 * -dmem_addr (uint32 offset) +dmem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset) { unsigned long phys; uint8 *mem; @@ -960,14 +974,14 @@ dmem_addr (uint32 offset) things like ``0xfffe + 0x0e60 == 0x10e5d''. Since offset's type is uint16 this is modulo'ed onto 0x0e5d. */ - phys_size = sim_cr16_translate_dmap_addr (offset, 1, &phys, NULL, + phys_size = sim_cr16_translate_dmap_addr (sd, cpu, offset, 1, &phys, NULL, dmap_register); if (phys_size == 0) { mem = State.mem.fault; } else - mem = map_memory (phys); + mem = map_memory (sd, cpu, phys); #ifdef DEBUG if ((cr16_debug & DEBUG_MEMORY)) { @@ -983,17 +997,17 @@ dmem_addr (uint32 offset) } uint8 * -imem_addr (uint32 offset) +imem_addr (SIM_DESC sd, SIM_CPU *cpu, uint32 offset) { unsigned long phys; uint8 *mem; - int phys_size = sim_cr16_translate_imap_addr (offset, 1, &phys, NULL, + int phys_size = sim_cr16_translate_imap_addr (sd, cpu, offset, 1, &phys, NULL, imap_register); if (phys_size == 0) { return State.mem.fault; } - mem = map_memory (phys); + mem = map_memory (sd, cpu, phys); #ifdef DEBUG if ((cr16_debug & DEBUG_MEMORY)) { @@ -1022,6 +1036,7 @@ sim_stop (SIM_DESC sd) void sim_resume (SIM_DESC sd, int step, int siggnal) { + SIM_CPU *cpu = STATE_CPU (sd, 0); uint32 curr_ins_size = 0; uint64 mcode = 0; uint8 *iaddr; @@ -1061,7 +1076,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) do { - iaddr = imem_addr ((uint32)PC); + iaddr = imem_addr (sd, cpu, (uint32)PC); if (iaddr == State.mem.fault) { #ifdef SIGBUS @@ -1076,7 +1091,7 @@ sim_resume (SIM_DESC sd, int step, int siggnal) State.pc_changed = 0; - curr_ins_size = do_run(sd, mcode); + curr_ins_size = do_run (sd, cpu, mcode); #if CR16_DEBUG (*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode); @@ -1138,7 +1153,10 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, char **argv, char **env) if (cr16_debug) (*cr16_callback->printf_filtered) (cr16_callback, "sim_create_inferior: PC=0x%lx\n", (long) start_address); #endif - SET_CREG (PC_CR, start_address); + { + SIM_CPU *cpu = STATE_CPU (sd, 0); + SET_CREG (PC_CR, start_address); + } SLOT_FLUSH (); return SIM_RC_OK; @@ -1265,6 +1283,7 @@ cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) static int cr16_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length) { + SIM_DESC sd = CPU_STATE (cpu); int size; switch ((enum sim_cr16_regs) rn) { diff --git a/sim/cr16/simops.c b/sim/cr16/simops.c index a923192..b452ee0 100644 --- a/sim/cr16/simops.c +++ b/sim/cr16/simops.c @@ -168,7 +168,7 @@ static int cond_stat(int cc) creg_t -move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) +move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p) { /* A MASK bit is set when the corresponding bit in the CR should be left alone. */ @@ -200,12 +200,13 @@ move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) } #ifdef DEBUG -static void trace_input_func (const char *name, +static void trace_input_func (SIM_DESC sd, + const char *name, enum op_types in1, enum op_types in2, enum op_types in3); -#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0) +#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0) #ifndef SIZE_INSTRUCTION #define SIZE_INSTRUCTION 8 @@ -232,7 +233,7 @@ static void trace_input_func (const char *name, #endif static void -trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum op_types in3) +trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3) { char *comma; enum op_types in[3]; @@ -264,21 +265,19 @@ trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum o else { - extern SIM_DESC trace_sd; - buf[0] = '\0'; byte_pc = PC; - if (STATE_TEXT_SECTION (trace_sd) - && byte_pc >= STATE_TEXT_START (trace_sd) - && byte_pc < STATE_TEXT_END (trace_sd)) + if (STATE_TEXT_SECTION (sd) + && byte_pc >= STATE_TEXT_START (sd) + && byte_pc < STATE_TEXT_END (sd)) { filename = (const char *)0; functionname = (const char *)0; linenumber = 0; - if (bfd_find_nearest_line (STATE_PROG_BFD (trace_sd), - STATE_TEXT_SECTION (trace_sd), + if (bfd_find_nearest_line (STATE_PROG_BFD (sd), + STATE_TEXT_SECTION (sd), (struct bfd_symbol **)0, - byte_pc - STATE_TEXT_START (trace_sd), + byte_pc - STATE_TEXT_START (sd), &filename, &functionname, &linenumber)) { p = buf; @@ -447,13 +446,13 @@ trace_input_func (const char *name, enum op_types in1, enum op_types in2, enum o } static void -do_trace_output_flush (void) +do_trace_output_flush (SIM_DESC sd) { (*cr16_callback->flush_stdout) (cr16_callback); } static void -do_trace_output_finish (void) +do_trace_output_finish (SIM_DESC sd) { (*cr16_callback->printf_filtered) (cr16_callback, " F0=%d F1=%d C=%d\n", @@ -465,7 +464,7 @@ do_trace_output_finish (void) #if 0 static void -trace_output_40 (uint64 val) +trace_output_40 (SIM_DESC sd, uint64 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { @@ -481,7 +480,7 @@ trace_output_40 (uint64 val) #endif static void -trace_output_32 (uint32 val) +trace_output_32 (SIM_DESC sd, uint32 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { @@ -490,12 +489,12 @@ trace_output_32 (uint32 val) SIZE_VALUES - 10, "", (int) val); - do_trace_output_finish (); + do_trace_output_finish (sd); } } static void -trace_output_16 (uint16 val) +trace_output_16 (SIM_DESC sd, uint16 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { @@ -504,22 +503,22 @@ trace_output_16 (uint16 val) SIZE_VALUES - 6, "", (int) val); - do_trace_output_finish (); + do_trace_output_finish (sd); } } static void -trace_output_void (void) +trace_output_void (SIM_DESC sd) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { (*cr16_callback->printf_filtered) (cr16_callback, "\n"); - do_trace_output_flush (); + do_trace_output_flush (sd); } } static void -trace_output_flag (void) +trace_output_flag (SIM_DESC sd) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { @@ -527,7 +526,7 @@ trace_output_flag (void) " :: %*s", SIZE_VALUES, ""); - do_trace_output_finish (); + do_trace_output_finish (sd); } } @@ -541,7 +540,7 @@ trace_output_flag (void) /* addub. */ void -OP_2C_8 (void) +OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp; uint8 a = OP[0] & 0xff; @@ -549,72 +548,72 @@ OP_2C_8 (void) trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a + b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addub. */ void -OP_2CB_C (void) +OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp; uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID); tmp = (a + b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addub. */ void -OP_2D_8 (void) +OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xff; uint8 b = (GPR (OP[1])) & 0xff; uint16 tmp = (a + b) & 0xff; trace_input ("addub", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2E_8 (void) +OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2EB_C (void) +OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2F_8 (void) +OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_30_8 (void) +OP_30_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1]) & 0xff); @@ -623,12 +622,12 @@ OP_30_8 (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_30B_C (void) +OP_30B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint8 b = (GPR (OP[1]) & 0xff); @@ -637,12 +636,12 @@ OP_30B_C (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_31_8 (void) +OP_31_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0]) & 0xff); uint8 b = (GPR (OP[1]) & 0xff); @@ -651,12 +650,12 @@ OP_31_8 (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_32_8 (void) +OP_32_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 tmp, b = GPR (OP[1]); @@ -665,12 +664,12 @@ OP_32_8 (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_32B_C (void) +OP_32B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 tmp, b = GPR (OP[1]); @@ -679,12 +678,12 @@ OP_32B_C (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_33_8 (void) +OP_33_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("addw", OP_REG, OP_REG, OP_VOID); @@ -692,12 +691,12 @@ OP_33_8 (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_34_8 (void) +OP_34_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG); @@ -705,12 +704,12 @@ OP_34_8 (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_34B_C (void) +OP_34B_C (SIM_DESC sd, SIM_CPU *cpu) { int8 a = OP[0] & 0xff; uint8 b = (GPR (OP[1])) & 0xff; @@ -719,12 +718,12 @@ OP_34B_C (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_35_8 (void) +OP_35_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xff; uint8 b = (GPR (OP[1])) & 0xff; @@ -733,12 +732,12 @@ OP_35_8 (void) SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_36_8 (void) +OP_36_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -747,12 +746,12 @@ OP_36_8 (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_36B_C (void) +OP_36B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -761,12 +760,12 @@ OP_36B_C (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_37_8 (void) +OP_37_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[1]); uint16 b = GPR (OP[1]); @@ -775,12 +774,12 @@ OP_37_8 (void) SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addd. */ void -OP_60_8 (void) +OP_60_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = (OP[0]); uint32 b = GPR32 (OP[1]); @@ -789,12 +788,12 @@ OP_60_8 (void) SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_60B_C (void) +OP_60B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = (SEXT16(OP[0])); uint32 b = GPR32 (OP[1]); @@ -803,26 +802,26 @@ OP_60B_C (void) SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_61_8 (void) +OP_61_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 b = GPR32 (OP[1]); uint32 tmp = (a + b); trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); } /* addd. */ void -OP_4_8 (void) +OP_4_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -832,12 +831,12 @@ OP_4_8 (void) SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_2_C (void) +OP_2_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -847,145 +846,145 @@ OP_2_C (void) SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* andb. */ void -OP_20_8 (void) +OP_20_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andb. */ void -OP_20B_C (void) +OP_20B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andb. */ void -OP_21_8 (void) +OP_21_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_REG, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_22_8 (void) +OP_22_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = OP[0], b = GPR (OP[1]); trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_22B_C (void) +OP_22B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = OP[0], b = GPR (OP[1]); trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_23_8 (void) +OP_23_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]); trace_input ("andw", OP_REG, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andd. */ void -OP_4_C (void) +OP_4_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = OP[0], b = GPR32 (OP[1]); trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID); tmp = a & b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* andd. */ void -OP_14B_14 (void) +OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1])); trace_input ("andd", OP_REGP, OP_REGP, OP_VOID); tmp = a & b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ord. */ void -OP_5_C (void) +OP_5_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID); tmp = a | b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ord. */ void -OP_149_14 (void) +OP_149_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); trace_input ("ord", OP_REGP, OP_REGP, OP_VOID); tmp = a | b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* xord. */ void -OP_6_C (void) +OP_6_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* xord. */ void -OP_14A_14 (void) +OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); trace_input ("xord", OP_REGP, OP_REGP, OP_VOID); tmp = a ^ b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_1_4 (void) +OP_1_4 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID); @@ -1002,19 +1001,19 @@ OP_1_4 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_18_8 (void) +OP_18_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID); @@ -1031,19 +1030,19 @@ OP_18_8 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_10_10 (void) +OP_10_10 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID); @@ -1060,19 +1059,19 @@ OP_10_10 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* bal. */ void -OP_C0_8 (void) +OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("bal", OP_REG, OP_DISP17, OP_VOID); @@ -1090,19 +1089,19 @@ OP_C0_8 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* bal. */ void -OP_102_14 (void) +OP_102_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID); @@ -1119,18 +1118,18 @@ OP_102_14 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jal. */ void -OP_148_14 (void) +OP_148_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jal", OP_REGP, OP_REGP, OP_VOID); @@ -1144,19 +1143,19 @@ OP_148_14 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jal. */ void -OP_D_C (void) +OP_D_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jal", OP_REGP, OP_VOID, OP_VOID); @@ -1170,19 +1169,19 @@ OP_D_C (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* beq0b. */ void -OP_C_8 (void) +OP_C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (GPR (OP[0]) & 0xFF); @@ -1198,12 +1197,12 @@ OP_C_8 (void) JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* bne0b. */ void -OP_D_8 (void) +OP_D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (GPR (OP[0]) & 0xFF); @@ -1219,12 +1218,12 @@ OP_D_8 (void) JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* beq0w. */ void -OP_E_8 (void) +OP_E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -1240,12 +1239,12 @@ OP_E_8 (void) JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* bne0w. */ void -OP_F_8 (void) +OP_F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -1261,13 +1260,13 @@ OP_F_8 (void) JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* jeq. */ void -OP_A0_C (void) +OP_A0_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID); @@ -1276,12 +1275,12 @@ OP_A0_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jne. */ void -OP_A1_C (void) +OP_A1_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jne", OP_REGP, OP_VOID, OP_VOID); @@ -1290,12 +1289,12 @@ OP_A1_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jcs. */ void -OP_A2_C (void) +OP_A2_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID); @@ -1304,12 +1303,12 @@ OP_A2_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jcc. */ void -OP_A3_C (void) +OP_A3_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID); @@ -1318,12 +1317,12 @@ OP_A3_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jhi. */ void -OP_A4_C (void) +OP_A4_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID); @@ -1332,12 +1331,12 @@ OP_A4_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jls. */ void -OP_A5_C (void) +OP_A5_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jls", OP_REGP, OP_VOID, OP_VOID); @@ -1346,12 +1345,12 @@ OP_A5_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jgt. */ void -OP_A6_C (void) +OP_A6_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID); @@ -1360,12 +1359,12 @@ OP_A6_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jle. */ void -OP_A7_C (void) +OP_A7_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jle", OP_REGP, OP_VOID, OP_VOID); @@ -1374,13 +1373,13 @@ OP_A7_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jfs. */ void -OP_A8_C (void) +OP_A8_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID); @@ -1389,12 +1388,12 @@ OP_A8_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jfc. */ void -OP_A9_C (void) +OP_A9_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID); @@ -1403,12 +1402,12 @@ OP_A9_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jlo. */ void -OP_AA_C (void) +OP_AA_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID); @@ -1417,12 +1416,12 @@ OP_AA_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jhs. */ void -OP_AB_C (void) +OP_AB_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID); @@ -1431,12 +1430,12 @@ OP_AB_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jlt. */ void -OP_AC_C (void) +OP_AC_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID); @@ -1445,12 +1444,12 @@ OP_AC_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jge. */ void -OP_AD_C (void) +OP_AD_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = 0; trace_input ("jge", OP_REGP, OP_VOID, OP_VOID); @@ -1459,203 +1458,203 @@ OP_AD_C (void) tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jump. */ void -OP_AE_C (void) +OP_AE_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jump", OP_REGP, OP_VOID, OP_VOID); tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jusr. */ void -OP_AF_C (void) +OP_AF_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID); tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ SET_PSR_U(1); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* seq. */ void -OP_80_C (void) +OP_80_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("seq", OP_REG, OP_VOID, OP_VOID); if ((PSR_Z) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sne. */ void -OP_81_C (void) +OP_81_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sne", OP_REG, OP_VOID, OP_VOID); if ((PSR_Z) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* scs. */ void -OP_82_C (void) +OP_82_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("scs", OP_REG, OP_VOID, OP_VOID); if ((PSR_C) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* scc. */ void -OP_83_C (void) +OP_83_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("scc", OP_REG, OP_VOID, OP_VOID); if ((PSR_C) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* shi. */ void -OP_84_C (void) +OP_84_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("shi", OP_REG, OP_VOID, OP_VOID); if ((PSR_L) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sls. */ void -OP_85_C (void) +OP_85_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sls", OP_REG, OP_VOID, OP_VOID); if ((PSR_L) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sgt. */ void -OP_86_C (void) +OP_86_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sgt", OP_REG, OP_VOID, OP_VOID); if ((PSR_N) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sle. */ void -OP_87_C (void) +OP_87_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sle", OP_REG, OP_VOID, OP_VOID); if ((PSR_N) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sfs. */ void -OP_88_C (void) +OP_88_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sfs", OP_REG, OP_VOID, OP_VOID); if ((PSR_F) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sfc. */ void -OP_89_C (void) +OP_89_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sfc", OP_REG, OP_VOID, OP_VOID); if ((PSR_F) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* slo. */ void -OP_8A_C (void) +OP_8A_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("slo", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_L) == 0)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* shs. */ void -OP_8B_C (void) +OP_8B_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("shs", OP_REG, OP_VOID, OP_VOID); if ( ((PSR_Z) == 1) | ((PSR_L) == 1)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* slt. */ void -OP_8C_C (void) +OP_8C_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("slt", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_N) == 0)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sge. */ void -OP_8D_C (void) +OP_8D_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sge", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 1) | ((PSR_N) == 1)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* cbitb. */ void -OP_D7_9 (void) +OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1664,12 +1663,12 @@ OP_D7_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitb. */ void -OP_107_14 (void) +OP_107_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1678,12 +1677,12 @@ OP_107_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitb. */ void -OP_68_8 (void) +OP_68_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1692,12 +1691,12 @@ OP_68_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_1AA_A (void) +OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1706,12 +1705,12 @@ OP_1AA_A (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_104_14 (void) +OP_104_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1720,12 +1719,12 @@ OP_104_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_D4_9 (void) +OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1734,12 +1733,12 @@ OP_D4_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_D6_9 (void) +OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1748,13 +1747,13 @@ OP_D6_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_105_14 (void) +OP_105_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1763,12 +1762,12 @@ OP_105_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_106_14 (void) +OP_106_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1777,13 +1776,13 @@ OP_106_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_6F_8 (void) +OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -1792,12 +1791,12 @@ OP_6F_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitw. */ void -OP_117_14 (void) +OP_117_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -1806,12 +1805,12 @@ OP_117_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitw. */ void -OP_36_7 (void) +OP_36_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -1826,13 +1825,13 @@ OP_36_7 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_1AB_A (void) +OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1841,12 +1840,12 @@ OP_1AB_A (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_114_14 (void) +OP_114_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1855,13 +1854,13 @@ OP_114_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_6E_8 (void) +OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1870,12 +1869,12 @@ OP_6E_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_69_8 (void) +OP_69_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1884,13 +1883,13 @@ OP_69_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_115_14 (void) +OP_115_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1899,12 +1898,12 @@ OP_115_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_116_14 (void) +OP_116_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1913,12 +1912,12 @@ OP_116_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitb. */ void -OP_E7_9 (void) +OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1927,12 +1926,12 @@ OP_E7_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_10B_14 (void) +OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1941,12 +1940,12 @@ OP_10B_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_70_8 (void) +OP_70_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1955,12 +1954,12 @@ OP_70_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_1CA_A (void) +OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1969,12 +1968,12 @@ OP_1CA_A (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_108_14 (void) +OP_108_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1983,13 +1982,13 @@ OP_108_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_E4_9 (void) +OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1998,12 +1997,12 @@ OP_E4_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_E6_9 (void) +OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2012,13 +2011,13 @@ OP_E6_9 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_109_14 (void) +OP_109_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2027,13 +2026,13 @@ OP_109_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_10A_14 (void) +OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2042,13 +2041,13 @@ OP_10A_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_77_8 (void) +OP_77_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -2057,12 +2056,12 @@ OP_77_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_11B_14 (void) +OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -2071,12 +2070,12 @@ OP_11B_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_3A_7 (void) +OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -2091,12 +2090,12 @@ OP_3A_7 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_1CB_A (void) +OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2105,12 +2104,12 @@ OP_1CB_A (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_118_14 (void) +OP_118_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -2119,12 +2118,12 @@ OP_118_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_76_8 (void) +OP_76_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2133,12 +2132,12 @@ OP_76_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_71_8 (void) +OP_71_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2147,12 +2146,12 @@ OP_71_8 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_119_14 (void) +OP_119_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2161,12 +2160,12 @@ OP_119_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_11A_14 (void) +OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2175,147 +2174,147 @@ OP_11A_14 (void) SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F7_9 (void) +OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitb. */ void -OP_10F_14 (void) +OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitb. */ void -OP_78_8 (void) +OP_78_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_1EA_A (void) +OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10C_14 (void) +OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F4_9 (void) +OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F6_9 (void) +OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10D_14 (void) +OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10E_14 (void) +OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_7F_8 (void) +OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitw. */ void -OP_11F_14 (void) +OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitw. */ void -OP_3E_7 (void) +OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -2328,109 +2327,109 @@ OP_3E_7 (void) tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_1EB_A (void) +OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11C_14 (void) +OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_7E_8 (void) +OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_79_8 (void) +OP_79_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11D_14 (void) +OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11E_14 (void) +OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbit. */ void -OP_6_8 (void) +OP_6_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); SET_PSR_F (b & (1 << a)); - trace_output_16 (b); + trace_output_16 (sd, b); } /* tbit. */ void -OP_7_8 (void) +OP_7_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_REG, OP_REG, OP_VOID); SET_PSR_F (b & (1 << a)); - trace_output_16 (b); + trace_output_16 (sd, b); } /* cmpb. */ void -OP_50_8 (void) +OP_50_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2438,12 +2437,12 @@ OP_50_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpb. */ void -OP_50B_C (void) +OP_50B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2451,12 +2450,12 @@ OP_50B_C (void) SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpb. */ void -OP_51_8 (void) +OP_51_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2464,12 +2463,12 @@ OP_51_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_52_8 (void) +OP_52_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint16 b = GPR (OP[1]); @@ -2477,12 +2476,12 @@ OP_52_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_52B_C (void) +OP_52B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint16 b = GPR (OP[1]); @@ -2490,12 +2489,12 @@ OP_52B_C (void) SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_53_8 (void) +OP_53_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]) ; uint16 b = GPR (OP[1]) ; @@ -2503,12 +2502,12 @@ OP_53_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_56_8 (void) +OP_56_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (OP[0]); uint32 b = GPR32 (OP[1]); @@ -2516,12 +2515,12 @@ OP_56_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_56B_C (void) +OP_56B_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (SEXT16(OP[0])); uint32 b = GPR32 (OP[1]); @@ -2529,12 +2528,12 @@ OP_56B_C (void) SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_57_8 (void) +OP_57_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]) ; uint32 b = GPR32 (OP[1]) ; @@ -2542,12 +2541,12 @@ OP_57_8 (void) SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_9_C (void) +OP_9_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (OP[0]); uint32 b = GPR32 (OP[1]); @@ -2555,168 +2554,168 @@ OP_9_C (void) SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* movb. */ void -OP_58_8 (void) +OP_58_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = OP[0] & 0xFF; uint16 a = (GPR (OP[1])) & 0xFF00; trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movb. */ void -OP_58B_C (void) +OP_58B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = OP[0] & 0xFF; uint16 a = (GPR (OP[1])) & 0xFF00; trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movb. */ void -OP_59_8 (void) +OP_59_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; uint16 a = (GPR (OP[1])) & 0xFF00; trace_input ("movb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5A_8 (void) +OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = OP[0]; trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5AB_C (void) +OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp = OP[0]; trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5B_8 (void) +OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); uint32 a = GPR32 (OP[1]); trace_input ("movw", OP_REG, OP_REGP, OP_VOID); a = (a & 0xffff0000) | tmp; SET_GPR32 (OP[1], a); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movxb. */ void -OP_5C_8 (void) +OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; trace_input ("movxb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movzb. */ void -OP_5D_8 (void) +OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; trace_input ("movzb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movxw. */ void -OP_5E_8 (void) +OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); trace_input ("movxw", OP_REG, OP_REGP, OP_VOID); SET_GPR32 (OP[1], SEXT16(tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movzw. */ void -OP_5F_8 (void) +OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); trace_input ("movzw", OP_REG, OP_REGP, OP_VOID); SET_GPR32 (OP[1], (tmp & 0x0000FFFF)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movd. */ void -OP_54_8 (void) +OP_54_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_54B_C (void) +OP_54B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = SEXT16(OP[0]); trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_55_8 (void) +OP_55_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = GPR32 (OP[0]); trace_input ("movd", OP_REGP, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_5_8 (void) +OP_5_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_7_C (void) +OP_7_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadm. */ void -OP_14_D (void) +OP_14_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR (0); uint16 count = OP[0], reg = 2, tmp; @@ -2725,7 +2724,7 @@ OP_14_D (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } @@ -2740,13 +2739,13 @@ OP_14_D (void) }; SET_GPR (0, addr); - trace_output_void (); + trace_output_void (sd); } /* loadmp. */ void -OP_15_D (void) +OP_15_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR32 (0); uint16 count = OP[0], reg = 2, tmp; @@ -2755,7 +2754,7 @@ OP_15_D (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } @@ -2770,13 +2769,13 @@ OP_15_D (void) }; SET_GPR32 (0, addr); - trace_output_void (); + trace_output_void (sd); } /* loadb. */ void -OP_88_8 (void) +OP_88_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb ABS20, REG * ADDR = zext24(abs20) | remap (ie 0xF00000) @@ -2792,12 +2791,12 @@ OP_88_8 (void) if (addr > 0xEFFFF) addr |= 0xF00000; tmp = (RB (addr)); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_127_14 (void) +OP_127_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb ABS24, REG * ADDR = abs24 @@ -2808,12 +2807,12 @@ OP_127_14 (void) trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_45_7 (void) +OP_45_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]ABS20 REG * ADDR = Rindex + zext24(disp20) @@ -2830,13 +2829,13 @@ OP_45_7 (void) tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_B_4 (void) +OP_B_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DIPS4(REGP) REG * ADDR = RPBASE + zext24(DISP4) @@ -2846,12 +2845,12 @@ OP_B_4 (void) trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_BE_8 (void) +OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -2870,12 +2869,12 @@ OP_BE_8 (void) tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_219_A (void) +OP_219_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp14(RPbasex) REG * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -2894,13 +2893,13 @@ OP_219_A (void) trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_184_14 (void) +OP_184_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DISPE20(REG) REG * zext24(Rbase) + zext24(dispe20) @@ -2911,12 +2910,12 @@ OP_184_14 (void) trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_124_14 (void) +OP_124_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DISP20(REG) REG * ADDR = zext24(Rbase) + zext24(disp20) @@ -2927,12 +2926,12 @@ OP_124_14 (void) trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_BF_8 (void) +OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb disp16(REGP) REG * ADDR = RPbase + zext24(disp16) @@ -2943,12 +2942,12 @@ OP_BF_8 (void) trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_125_14 (void) +OP_125_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb disp20(REGP) REG * ADDR = RPbase + zext24(disp20) @@ -2958,13 +2957,13 @@ OP_125_14 (void) trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_185_14 (void) +OP_185_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb -disp20(REGP) REG * ADDR = RPbase + zext24(-disp20) @@ -2974,12 +2973,12 @@ OP_185_14 (void) trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_126_14 (void) +OP_126_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp20(RPbasexb) REG * ADDR = RPbasex + Rindex + zext24(disp20) @@ -2998,13 +2997,13 @@ OP_126_14 (void) tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_89_8 (void) +OP_89_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw ABS20, REG * ADDR = zext24(abs20) | remap @@ -3020,13 +3019,13 @@ OP_89_8 (void) if (addr > 0xEFFFF) addr |= 0xF00000; tmp = (RW (addr)); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12F_14 (void) +OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw ABS24, REG * ADDR = abs24 @@ -3036,12 +3035,12 @@ OP_12F_14 (void) trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID); tmp = (RW (addr)); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_47_7 (void) +OP_47_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]ABS20 REG * ADDR = Rindex + zext24(disp20) @@ -3058,13 +3057,13 @@ OP_47_7 (void) tmp = (RW (addr)); SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9_4 (void) +OP_9_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw DIPS4(REGP) REGP * ADDR = RPBASE + zext24(DISP4) @@ -3082,13 +3081,13 @@ OP_9_4 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9E_8 (void) +OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -3107,13 +3106,13 @@ OP_9E_8 (void) tmp = RW (addr); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_21B_A (void) +OP_21B_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp14(RPbasex) REG * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -3131,12 +3130,12 @@ OP_21B_A (void) tmp = (RW (addr)); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_18C_14 (void) +OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw dispe20(REG) REGP * REGP = [DISPE20+[REG]] */ @@ -3154,13 +3153,13 @@ OP_18C_14 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12C_14 (void) +OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw DISP20(REG) REGP * ADDR = zext24(Rbase) + zext24(disp20) @@ -3179,12 +3178,12 @@ OP_12C_14 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9F_8 (void) +OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw disp16(REGP) REGP * ADDR = RPbase + zext24(disp16) @@ -3202,12 +3201,12 @@ OP_9F_8 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12D_14 (void) +OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw disp20(REGP) REGP * ADDR = RPbase + zext24(disp20) @@ -3225,12 +3224,12 @@ OP_12D_14 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_18D_14 (void) +OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw -disp20(REGP) REG * ADDR = RPbase + zext24(-disp20) @@ -3249,13 +3248,13 @@ OP_18D_14 (void) else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12E_14 (void) +OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp20(RPbasexb) REG * ADDR = RPbasex + Rindex + zext24(disp20) @@ -3272,13 +3271,13 @@ OP_12E_14 (void) tmp = (RW (addr)); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadd. */ void -OP_87_8 (void) +OP_87_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd ABS20, REGP * ADDR = zext24(abs20) | remap @@ -3295,12 +3294,12 @@ OP_87_8 (void) tmp = RLW (addr); tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_12B_14 (void) +OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd ABS24, REGP * ADDR = abs24 @@ -3312,13 +3311,13 @@ OP_12B_14 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[1],tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_46_7 (void) +OP_46_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]ABS20 REGP * ADDR = Rindex + zext24(disp20) @@ -3335,13 +3334,13 @@ OP_46_7 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_A_4 (void) +OP_A_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd dips4(regp) REGP * ADDR = Rpbase + zext24(disp4) @@ -3352,13 +3351,13 @@ OP_A_4 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_AE_8 (void) +OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp0(RPbasex) REGP * ADDR = Rpbasex + Rindex @@ -3375,13 +3374,13 @@ OP_AE_8 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[3], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_21A_A (void) +OP_21A_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp14(RPbasex) REGP * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -3398,13 +3397,13 @@ OP_21A_A (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR (OP[3],tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_188_14 (void) +OP_188_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd dispe20(REG) REG * zext24(Rbase) + zext24(dispe20) @@ -3415,13 +3414,13 @@ OP_188_14 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_128_14 (void) +OP_128_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd DISP20(REG) REG * ADDR = zext24(Rbase) + zext24(disp20) @@ -3432,12 +3431,12 @@ OP_128_14 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_AF_8 (void) +OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd disp16(REGP) REGP * ADDR = RPbase + zext24(disp16) @@ -3447,13 +3446,13 @@ OP_AF_8 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_129_14 (void) +OP_129_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd disp20(REGP) REGP * ADDR = RPbase + zext24(disp20) @@ -3463,12 +3462,12 @@ OP_129_14 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_189_14 (void) +OP_189_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd -disp20(REGP) REGP * ADDR = RPbase + zext24(-disp20) @@ -3479,12 +3478,12 @@ OP_189_14 (void) tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_12A_14 (void) +OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp20(RPbasexb) REGP * ADDR = RPbasex + Rindex + zext24(disp20) @@ -3501,13 +3500,13 @@ OP_12A_14 (void) tmp = RLW (addr); tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[3], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* storb. */ void -OP_C8_8 (void) +OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, ABS20 * ADDR = zext24(abs20) | remap @@ -3521,12 +3520,12 @@ OP_C8_8 (void) uint32 addr = OP[1]; trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_137_14 (void) +OP_137_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, ABS24 * ADDR = abs24 @@ -3536,12 +3535,12 @@ OP_137_14 (void) uint32 addr = OP[1]; trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_65_7 (void) +OP_65_7 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]ABS20 * ADDR = Rindex + zext24(disp20) @@ -3557,12 +3556,12 @@ OP_65_7 (void) addr = (GPR32 (13)) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_F_4 (void) +OP_F_4 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DIPS4(REGP) * ADDR = RPBASE + zext24(DISP4) @@ -3572,12 +3571,12 @@ OP_F_4 (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_FE_8 (void) +OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -3593,12 +3592,12 @@ OP_FE_8 (void) addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_319_A (void) +OP_319_A (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]disp14(RPbasex) * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -3608,12 +3607,12 @@ OP_319_A (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_194_14 (void) +OP_194_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DISPE20(REG) * zext24(Rbase) + zext24(dispe20) @@ -3623,12 +3622,12 @@ OP_194_14 (void) uint32 addr = OP[1] + (GPR (OP[2])); trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_134_14 (void) +OP_134_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DISP20(REG) * ADDR = zext24(Rbase) + zext24(disp20) @@ -3638,12 +3637,12 @@ OP_134_14 (void) uint32 addr = OP[1] + (GPR (OP[2])); trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_FF_8 (void) +OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, disp16(REGP) * ADDR = RPbase + zext24(disp16) @@ -3653,12 +3652,12 @@ OP_FF_8 (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_135_14 (void) +OP_135_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, disp20(REGP) * ADDR = RPbase + zext24(disp20) @@ -3668,12 +3667,12 @@ OP_135_14 (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_195_14 (void) +OP_195_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, -disp20(REGP) * ADDR = RPbase + zext24(-disp20) @@ -3683,12 +3682,12 @@ OP_195_14 (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_136_14 (void) +OP_136_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]disp20(RPbase) * ADDR = RPbasex + Rindex + zext24(disp20) @@ -3698,35 +3697,35 @@ OP_136_14 (void) uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* STR_IMM instructions. */ /* storb . */ void -OP_81_8 (void) +OP_81_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = OP[1]; trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_123_14 (void) +OP_123_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = OP[1]; trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_42_7 (void) +OP_42_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (OP[0]) & 0xff; @@ -3738,101 +3737,101 @@ OP_42_7 (void) addr = (GPR32 (13)) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_218_A (void) +OP_218_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_82_8 (void) +OP_82_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_120_14 (void) +OP_120_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_83_8 (void) +OP_83_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_121_14 (void) +OP_121_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_122_14 (void) +OP_122_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* endif for STR_IMM. */ /* storw . */ void -OP_C9_8 (void) +OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint32 addr = OP[1]; trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13F_14 (void) +OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint32 addr = OP[1]; trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_67_7 (void) +OP_67_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -3844,135 +3843,135 @@ OP_67_7 (void) addr = (GPR32 (13)) + OP[2]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_D_4 (void) +OP_D_4 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_DE_8 (void) +OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_31B_A (void) +OP_31B_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_19C_14 (void) +OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13C_14 (void) +OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_DF_8 (void) +OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13D_14 (void) +OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_19D_14 (void) +OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13E_14 (void) +OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* STORE-w IMM instruction *****/ /* storw . */ void -OP_C1_8 (void) +OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1]; trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_133_14 (void) +OP_133_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1]; trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_62_7 (void) +OP_62_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = OP[0]; @@ -3984,102 +3983,102 @@ OP_62_7 (void) addr = (GPR32 (13)) + OP[2]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_318_A (void) +OP_318_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_C2_8 (void) +OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_130_14 (void) +OP_130_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_C3_8 (void) +OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_131_14 (void) +OP_131_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_132_14 (void) +OP_132_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_C7_8 (void) +OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = OP[1]; trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_13B_14 (void) +OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = OP[1]; trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_66_7 (void) +OP_66_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr, a = GPR32 (OP[0]); trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID); @@ -4090,111 +4089,111 @@ OP_66_7 (void) addr = (GPR32 (13)) + OP[2]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_E_4 (void) +OP_E_4 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_EE_8 (void) +OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_31A_A (void) +OP_31A_A (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_198_14 (void) +OP_198_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_138_14 (void) +OP_138_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_EF_8 (void) +OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_139_14 (void) +OP_139_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_199_14 (void) +OP_199_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_13A_14 (void) +OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID); SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* macqu. */ void -OP_14D_14 (void) +OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 src1, src2; @@ -4204,12 +4203,12 @@ OP_14D_14 (void) tmp = src1 * src2; /*REVISIT FOR SATURATION and Q FORMAT. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* macuw. */ void -OP_14E_14 (void) +OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; uint16 src1, src2; @@ -4219,12 +4218,12 @@ OP_14E_14 (void) tmp = src1 * src2; /*REVISIT FOR SATURATION. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* macsw. */ void -OP_14F_14 (void) +OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 src1, src2; @@ -4234,13 +4233,13 @@ OP_14F_14 (void) tmp = src1 * src2; /*REVISIT FOR SATURATION. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulb. */ void -OP_64_8 (void) +OP_64_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (OP[0]) & 0xff; @@ -4248,38 +4247,38 @@ OP_64_8 (void) trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulb. */ void -OP_64B_C (void) +OP_64B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulb. */ void -OP_65_8 (void) +OP_65_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulb", OP_REG, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulw. */ void -OP_66_8 (void) +OP_66_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; uint16 a = OP[0]; @@ -4287,75 +4286,75 @@ OP_66_8 (void) trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulw. */ void -OP_66B_C (void) +OP_66B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = OP[0], b = (GPR (OP[1])); trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulw. */ void -OP_67_8 (void) +OP_67_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("mulw", OP_REG, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulsb. */ void -OP_B_8 (void) +OP_B_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulsb", OP_REG, OP_REG, OP_VOID); tmp = a * b; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulsw. */ void -OP_62_8 (void) +OP_62_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* muluw. */ void -OP_63_8 (void) +OP_63_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* nop. */ void -OP_2C00_10 (void) +OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); @@ -4371,81 +4370,81 @@ OP_2C00_10 (void) } #endif - trace_output_void (); + trace_output_void (sd); } /* orb. */ void -OP_24_8 (void) +OP_24_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orb. */ void -OP_24B_C (void) +OP_24B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orb. */ void -OP_25_8 (void) +OP_25_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_REG, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_26_8 (void) +OP_26_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_26B_C (void) +OP_26B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_27_8 (void) +OP_27_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("orw", OP_REG, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshb. */ void -OP_13_9 (void) +OP_13_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4460,12 +4459,12 @@ OP_13_9 (void) sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshb. */ void -OP_44_8 (void) +OP_44_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])) & 0xff; uint16 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4486,12 +4485,12 @@ OP_44_8 (void) sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshw. */ void -OP_46_8 (void) +OP_46_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, b = GPR (OP[1]); int16 a = GPR (OP[0]); @@ -4512,12 +4511,12 @@ OP_46_8 (void) sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshw. */ void -OP_49_8 (void) +OP_49_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4531,12 +4530,12 @@ OP_49_8 (void) sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshd. */ void -OP_25_7 (void) +OP_25_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, b = GPR32 (OP[1]); uint16 a = OP[0]; @@ -4551,12 +4550,12 @@ OP_25_7 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* lshd. */ void -OP_47_8 (void) +OP_47_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, b = GPR32 (OP[1]); uint16 a = GPR (OP[0]); @@ -4577,12 +4576,12 @@ OP_47_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashub. */ void -OP_80_9 (void) +OP_80_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4597,12 +4596,12 @@ OP_80_9 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashub. */ void -OP_81_9 (void) +OP_81_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4617,13 +4616,13 @@ OP_81_9 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashub. */ void -OP_41_8 (void) +OP_41_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = (GPR (OP[0])); int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4646,13 +4645,13 @@ OP_41_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_42_8 (void) +OP_42_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4667,12 +4666,12 @@ OP_42_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_43_8 (void) +OP_43_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4686,12 +4685,12 @@ OP_43_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_45_8 (void) +OP_45_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int16 a = GPR (OP[0]), b = GPR (OP[1]); @@ -4713,12 +4712,12 @@ OP_45_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashud. */ void -OP_26_7 (void) +OP_26_7 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp,b = GPR32 (OP[1]); uint32 a = OP[0]; @@ -4732,12 +4731,12 @@ OP_26_7 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashud. */ void -OP_27_7 (void) +OP_27_7 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int32 a = OP[0], b = GPR32 (OP[1]); @@ -4751,12 +4750,12 @@ OP_27_7 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashud. */ void -OP_48_8 (void) +OP_48_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]); @@ -4777,13 +4776,13 @@ OP_48_8 (void) sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* storm. */ void -OP_16_D (void) +OP_16_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR (1); uint16 count = OP[0], reg = 2; @@ -4792,7 +4791,7 @@ OP_16_D (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } @@ -4807,13 +4806,13 @@ OP_16_D (void) SET_GPR (1, addr); - trace_output_void (); + trace_output_void (sd); } /* stormp. */ void -OP_17_D (void) +OP_17_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR32 (6); uint16 count = OP[0], reg = 2; @@ -4822,7 +4821,7 @@ OP_17_D (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } @@ -4836,12 +4835,12 @@ OP_17_D (void) }; SET_GPR32 (6, addr); - trace_output_void (); + trace_output_void (sd); } /* subb. */ void -OP_38_8 (void) +OP_38_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1])) & 0xff; @@ -4852,12 +4851,12 @@ OP_38_8 (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subb. */ void -OP_38B_C (void) +OP_38B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -4868,12 +4867,12 @@ OP_38B_C (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subb. */ void -OP_39_8 (void) +OP_39_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -4884,12 +4883,12 @@ OP_39_8 (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3A_8 (void) +OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -4900,12 +4899,12 @@ OP_3A_8 (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3AB_C (void) +OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -4916,12 +4915,12 @@ OP_3AB_C (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp & 0xffff); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3B_8 (void) +OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = GPR (OP[1]); @@ -4932,12 +4931,12 @@ OP_3B_8 (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp & 0xffff); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3C_8 (void) +OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1])) & 0xff; @@ -4950,12 +4949,12 @@ OP_3C_8 (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3CB_C (void) +OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = (GPR (OP[1])) & 0xff; @@ -4968,12 +4967,12 @@ OP_3CB_C (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3D_8 (void) +OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])) & 0xff; uint16 b = (GPR (OP[1])) & 0xff; @@ -4985,12 +4984,12 @@ OP_3D_8 (void) SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3E_8 (void) +OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0], b = (GPR (OP[1])); uint16 tmp1 = a + (PSR_C); @@ -5001,12 +5000,12 @@ OP_3E_8 (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3EB_C (void) +OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -5018,12 +5017,12 @@ OP_3EB_C (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3F_8 (void) +OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); uint16 tmp1 = a + (PSR_C); @@ -5034,12 +5033,12 @@ OP_3F_8 (void) SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subd. */ void -OP_3_C (void) +OP_3_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -5051,12 +5050,12 @@ OP_3_C (void) SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* subd. */ void -OP_14C_14 (void) +OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 b = GPR32 (OP[1]); @@ -5068,12 +5067,12 @@ OP_14C_14 (void) SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* excp. */ void -OP_C_C (void) +OP_C_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; uint16 a; @@ -5144,7 +5143,7 @@ OP_C_C (void) /* Turn a pointer in a register into a pointer into real memory. */ -#define MEMPTR(x) ((char *)(dmem_addr(x))) +#define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x))) switch (FUNC) { @@ -5153,7 +5152,7 @@ OP_C_C (void) case TARGET_SYS_fork: trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); RETVAL (fork ()); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5161,14 +5160,14 @@ OP_C_C (void) case TARGET_SYS_getpid: trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); RETVAL (getpid ()); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_kill: trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); if (PARM1 == getpid ()) { - trace_output_void (); + trace_output_void (sd); State.exception = PARM2; } else @@ -5279,7 +5278,7 @@ OP_C_C (void) if (os_sig == -1) { - trace_output_void (); + trace_output_void (sd); (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2); (*cr16_callback->flush_stdout) (cr16_callback); State.exception = SIGILL; @@ -5287,7 +5286,7 @@ OP_C_C (void) else { RETVAL (kill (PARM1, PARM2)); - trace_output_16 (result); + trace_output_16 (sd, result); } } break; @@ -5297,7 +5296,7 @@ OP_C_C (void) trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID); RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3), (char **)MEMPTR (PARM4))); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5305,7 +5304,7 @@ OP_C_C (void) case TARGET_SYS_execv: trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID); RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5321,7 +5320,7 @@ OP_C_C (void) SW (buf, host_fd[0]); buf += sizeof(uint16); SW (buf, host_fd[1]); - trace_output_16 (result); + trace_output_16 (sd, result); } break; #endif @@ -5334,7 +5333,7 @@ OP_C_C (void) RETVAL (wait (&status)); if (PARM1) SW (PARM1, status); - trace_output_16 (result); + trace_output_16 (sd, result); } break; #endif @@ -5342,12 +5341,12 @@ OP_C_C (void) case TARGET_SYS_getpid: trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); RETVAL (1); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_kill: trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); - trace_output_void (); + trace_output_void (sd); State.exception = PARM2; break; #endif @@ -5357,14 +5356,14 @@ OP_C_C (void) RETVAL (cr16_callback->read (cr16_callback, PARM1, MEMPTR (((unsigned long)PARM3 << 16) |((unsigned long)PARM2)), PARM4)); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_write: trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG); RETVAL ((int)cr16_callback->write (cr16_callback, PARM1, MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4)); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_lseek: @@ -5372,13 +5371,13 @@ OP_C_C (void) RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1, ((((long) PARM3) << 16) | PARM2), PARM4)); - trace_output_32 (result); + trace_output_32 (sd, result); break; case TARGET_SYS_close: trace_input ("<close>", OP_REG, OP_VOID, OP_VOID); RETVAL (cr16_callback->close (cr16_callback, PARM1)); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_open: @@ -5386,7 +5385,7 @@ OP_C_C (void) RETVAL32 (cr16_callback->open (cr16_callback, MEMPTR ((((unsigned long)PARM2)<<16)|PARM1), PARM3)); - trace_output_32 (result); + trace_output_32 (sd, result); break; #ifdef TARGET_SYS_rename @@ -5395,27 +5394,27 @@ OP_C_C (void) RETVAL (cr16_callback->rename (cr16_callback, MEMPTR ((((unsigned long)PARM2)<<16) |PARM1), MEMPTR ((((unsigned long)PARM4)<<16) |PARM3))); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif case 0x408: /* REVISIT: Added a dummy getenv call. */ trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID); RETVAL32 (0); - trace_output_32 (result); + trace_output_32 (sd, result); break; case TARGET_SYS_exit: trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID); State.exception = SIG_CR16_EXIT; - trace_output_void (); + trace_output_void (sd); break; case TARGET_SYS_unlink: trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID); RETVAL (cr16_callback->unlink (cr16_callback, MEMPTR (((unsigned long)PARM2<<16)|PARM1))); - trace_output_16 (result); + trace_output_16 (sd, result); break; @@ -5446,7 +5445,7 @@ OP_C_C (void) SLW (buf+28, host_stat.st_mtime); SLW (buf+36, host_stat.st_ctime); } - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5454,14 +5453,14 @@ OP_C_C (void) case TARGET_SYS_chown: trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID); RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif case TARGET_SYS_chmod: trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID); RETVAL (chmod (MEMPTR (PARM1), PARM2)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #ifdef TARGET_SYS_utime @@ -5470,7 +5469,7 @@ OP_C_C (void) /* Cast the second argument to void *, to avoid type mismatch if a prototype is present. */ RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5478,7 +5477,7 @@ OP_C_C (void) case TARGET_SYS_time: trace_input ("<time>", OP_VOID, OP_VOID, OP_REG); RETVAL32 (time (NULL)); - trace_output_32 (result); + trace_output_32 (sd, result); break; #endif @@ -5490,11 +5489,11 @@ OP_C_C (void) State.exception = SIGTRAP; tmp = (PC); JMP(tmp); - trace_output_void (); + trace_output_void (sd); break; case SIGTRAP: /* supervisor call ? */ State.exception = SIG_CR16_EXIT; - trace_output_void (); + trace_output_void (sd); break; default: cr16_callback->error (cr16_callback, "Unknown syscall %d", FUNC); @@ -5513,7 +5512,7 @@ OP_C_C (void) /* push. */ void -OP_3_9 (void) +OP_3_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; uint32 tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0; @@ -5557,12 +5556,12 @@ OP_3_9 (void) sp_addr = (GPR32 (15)) - (a * 2) - 4; SET_GPR32 (15, sp_addr); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* push. */ void -OP_1_8 (void) +OP_1_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 sp_addr, tmp, is_regp = 0; uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; @@ -5614,26 +5613,26 @@ OP_1_8 (void) SET_GPR32 (15, sp_addr); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* push. */ void -OP_11E_10 (void) +OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu) { uint32 sp_addr = (GPR32 (15)), tmp; trace_input ("push", OP_VOID, OP_VOID, OP_VOID); tmp = (GPR32 (14)); SLW(sp_addr-4,tmp); /* Store RA address. */ SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* pop. */ void -OP_5_9 (void) +OP_5_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0;; @@ -5681,12 +5680,12 @@ OP_5_9 (void) SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* pop. */ void -OP_2_8 (void) +OP_2_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; uint32 tmp, sp_addr = (GPR32 (15)), is_regp = 0; @@ -5735,12 +5734,12 @@ OP_2_8 (void) SET_GPR32 (15, sp_addr); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* pop. */ void -OP_21E_10 (void) +OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu) { uint32 sp_addr = GPR32 (15); uint32 tmp; @@ -5750,40 +5749,40 @@ OP_21E_10 (void) SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */ - trace_output_void (); + trace_output_void (sd); } /* popret. */ void -OP_7_9 (void) +OP_7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0], b = OP[1]; trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG); - OP_5_9 (); + OP_5_9 (sd, cpu); JMP(((GPR32(14)) << 1) & 0xffffff); - trace_output_void (); + trace_output_void (sd); } /* popret. */ void -OP_3_8 (void) +OP_3_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0], b = OP[1]; trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID); - OP_2_8 (); + OP_2_8 (sd, cpu); JMP(((GPR32(14)) << 1) & 0xffffff); - trace_output_void (); + trace_output_void (sd); } /* popret. */ void -OP_31E_10 (void) +OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("popret", OP_VOID, OP_VOID, OP_VOID); - OP_21E_10 (); + OP_21E_10 (sd, cpu); tmp = (((GPR32(14)) << 1) & 0xffffff); /* If the resulting PC value is less than 0x00_0000 or greater than 0xFF_FFFF, this instruction causes an IAD trap.*/ @@ -5792,226 +5791,226 @@ OP_31E_10 (void) { State.exception = SIG_CR16_BUS; State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); + trace_output_void (sd); return; } else JMP (tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cinv[i]. */ void -OP_A_10 (void) +OP_A_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* cinv[i,u]. */ void -OP_B_10 (void) +OP_B_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* cinv[d]. */ void -OP_C_10 (void) +OP_C_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* cinv[d,u]. */ void -OP_D_10 (void) +OP_D_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* cinv[d,i]. */ void -OP_E_10 (void) +OP_E_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* cinv[d,i,u]. */ void -OP_F_10 (void) +OP_F_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* retx. */ void -OP_3_10 (void) +OP_3_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("retx", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* di. */ void -OP_4_10 (void) +OP_4_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("di", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* ei. */ void -OP_5_10 (void) +OP_5_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("ei", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* wait. */ void -OP_6_10 (void) +OP_6_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); State.exception = SIGTRAP; - trace_output_void (); + trace_output_void (sd); } /* ewait. */ void -OP_7_10 (void) +OP_7_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID); SET_PSR_I (1); - trace_output_void (); + trace_output_void (sd); } /* xorb. */ void -OP_28_8 (void) +OP_28_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* xorb. */ void -OP_28B_C (void) +OP_28B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* xorb. */ void -OP_29_8 (void) +OP_29_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("xorb", OP_REG, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* xorw. */ void -OP_2A_8 (void) +OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* xorw. */ void -OP_2AB_C (void) +OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* xorw. */ void -OP_2B_8 (void) +OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("xorw", OP_REG, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /*REVISIT FOR LPR/SPR . */ /* lpr. */ void -OP_140_14 (void) +OP_140_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); trace_input ("lpr", OP_REG, OP_REG, OP_VOID); SET_CREG (OP[1], a); - trace_output_16 (a); + trace_output_16 (sd, a); } /* lprd. */ void -OP_141_14 (void) +OP_141_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); trace_input ("lprd", OP_REGP, OP_REG, OP_VOID); SET_CREG (OP[1], a); - trace_output_flag (); + trace_output_flag (sd); } /* spr. */ void -OP_142_14 (void) +OP_142_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = CREG (OP[0]); trace_input ("spr", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], a); - trace_output_16 (a); + trace_output_16 (sd, a); } /* sprd. */ void -OP_143_14 (void) +OP_143_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = CREG (OP[0]); trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID); SET_GPR32 (OP[1], a); - trace_output_32 (a); + trace_output_32 (sd, a); } /* null. */ void -OP_0_20 (void) +OP_0_20 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("null", OP_VOID, OP_VOID, OP_VOID); State.exception = SIG_CR16_STOP;

[3/6] sim: cr16: push down sd/cpu vars [committed]

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Patch