From patchwork Fri Oct 2 11:23:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 8914 Received: (qmail 109596 invoked by alias); 2 Oct 2015 11:24:13 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 109526 invoked by uid 89); 2 Oct 2015 11:24:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-Spam-User: qpsmtpd, 2 recipients X-HELO: mail-pa0-f49.google.com Received: from mail-pa0-f49.google.com (HELO mail-pa0-f49.google.com) (209.85.220.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 02 Oct 2015 11:24:11 +0000 Received: by padhy16 with SMTP id hy16so104767174pad.1; Fri, 02 Oct 2015 04:24:09 -0700 (PDT) X-Received: by 10.66.138.11 with SMTP id qm11mr19448333pab.126.1443785049394; Fri, 02 Oct 2015 04:24:09 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com (power-aix.osuosl.org. [140.211.15.154]) by smtp.gmail.com with ESMTPSA id yq2sm11561338pbb.39.2015.10.02.04.24.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Oct 2015 04:24:09 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: marcus.shawcroft@gmail.com Cc: gdb-patches@sourceware.org, binutils@sourceware.org Subject: [PATCH 3/3] [aarch64] use aarch64_decode_insn to decode instructions in GDB Date: Fri, 2 Oct 2015 12:23:59 +0100 Message-Id: <1443785039-24602-4-git-send-email-yao.qi@linaro.org> In-Reply-To: <1443785039-24602-1-git-send-email-yao.qi@linaro.org> References: <1443785039-24602-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes In this patch, we start to use aarch64_decode_insn to decode instructions in aarch64_software_single_step. gdb: 2015-10-02 Yao Qi * aarch64-tdep.c: Include opcode/aarch64.h. (submask): Move it above. (bit): Likewise. (bits): Likewise. (aarch64_software_single_step): Call aarch64_decode_insn. Decode instruction by aarch64_inst instead of using aarch64_decode_bcond and decode_masked_match. --- gdb/aarch64-tdep.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 5b5e1ad..df67e12 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -59,6 +59,12 @@ #include "arch/aarch64-insn.h" +#include "opcode/aarch64.h" + +#define submask(x) ((1L << ((x) + 1)) - 1) +#define bit(obj,st) (((obj) >> (st)) & 1) +#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) + /* Pseudo register base numbers. */ #define AARCH64_Q0_REGNUM 0 #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32) @@ -2491,35 +2497,40 @@ aarch64_software_single_step (struct frame_info *frame) int insn_count; int bc_insn_count = 0; /* Conditional branch instruction count. */ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ + aarch64_inst inst; + + if (aarch64_decode_insn (insn, &inst) != 0) + return 0; /* Look for a Load Exclusive instruction which begins the sequence. */ - if (!decode_masked_match (insn, 0x3fc00000, 0x08400000)) + if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) return 0; for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) { - int32_t offset; - unsigned cond; - loc += insn_size; insn = read_memory_unsigned_integer (loc, insn_size, byte_order_for_code); + if (aarch64_decode_insn (insn, &inst) != 0) + return 0; /* Check if the instruction is a conditional branch. */ - if (aarch64_decode_bcond (loc, insn, &cond, &offset)) + if (inst.opcode->iclass == condbranch) { + gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); + if (bc_insn_count >= 1) return 0; /* It is, so we'll try to set a breakpoint at the destination. */ - breaks[1] = loc + offset; + breaks[1] = loc + inst.operands[0].imm.value; bc_insn_count++; last_breakpoint++; } /* Look for the Store Exclusive which closes the atomic sequence. */ - if (decode_masked_match (insn, 0x3fc00000, 0x08000000)) + if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) { closing_insn = loc; break; @@ -2771,10 +2782,6 @@ When on, AArch64 specific debugging is enabled."), /* AArch64 process record-replay related structures, defines etc. */ -#define submask(x) ((1L << ((x) + 1)) - 1) -#define bit(obj,st) (((obj) >> (st)) & 1) -#define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) - #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ do \ { \