From patchwork Thu May 28 14:20:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yao Qi X-Patchwork-Id: 6958 Received: (qmail 107088 invoked by alias); 28 May 2015 14:20:45 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 106996 invoked by uid 89); 28 May 2015 14:20:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-pa0-f47.google.com Received: from mail-pa0-f47.google.com (HELO mail-pa0-f47.google.com) (209.85.220.47) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 28 May 2015 14:20:31 +0000 Received: by pabru16 with SMTP id ru16so24668461pab.1 for ; Thu, 28 May 2015 07:20:30 -0700 (PDT) X-Received: by 10.66.249.1 with SMTP id yq1mr5835333pac.3.1432822829964; Thu, 28 May 2015 07:20:29 -0700 (PDT) Received: from E107787-LIN.cambridge.arm.com (gcc1-power7.osuosl.org. [140.211.15.137]) by mx.google.com with ESMTPSA id dd3sm2587101pad.45.2015.05.28.07.20.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 28 May 2015 07:20:29 -0700 (PDT) From: Yao Qi X-Google-Original-From: Yao Qi To: gdb-patches@sourceware.org Subject: [PATCH 5/6] Fetch and store FP registers by PTRACE_{G,S}ETREGSET Date: Thu, 28 May 2015 15:20:15 +0100 Message-Id: <1432822816-32327-6-git-send-email-yao.qi@linaro.org> In-Reply-To: <1432822816-32327-1-git-send-email-yao.qi@linaro.org> References: <1432822816-32327-1-git-send-email-yao.qi@linaro.org> X-IsSubscribed: yes If kernel supports PTRACE_GETREGSET, GDB uses PTRACE_{G,S}ETREGSET to fetch and store FP registers. gdb: 2015-05-28 Yao Qi * arm-linux-nat.c (fetch_fpregister): Use PTRACE_GETREGSET. (fetch_fpregs): Likewise. * arm-linux-nat.c (store_fpregister): Use PTRACE_SETREGSET. (store_fpregs): Likewise. --- gdb/arm-linux-nat.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 74 insertions(+), 7 deletions(-) diff --git a/gdb/arm-linux-nat.c b/gdb/arm-linux-nat.c index 0a86ed6..b74767c 100644 --- a/gdb/arm-linux-nat.c +++ b/gdb/arm-linux-nat.c @@ -88,12 +88,23 @@ fetch_fpregister (struct regcache *regcache, int regno) { int ret, tid; gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; - + /* Get the thread id for the ptrace call. */ tid = GET_THREAD_ID (inferior_ptid); /* Read the floating point state. */ - ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + struct iovec iov; + + iov.iov_base = &fp; + iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; + + ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to fetch floating point register.")); @@ -123,7 +134,18 @@ fetch_fpregs (struct regcache *regcache) tid = GET_THREAD_ID (inferior_ptid); /* Read the floating point state. */ - ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + struct iovec iov; + + iov.iov_base = &fp; + iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; + + ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to fetch the floating point registers.")); @@ -152,7 +174,18 @@ store_fpregister (const struct regcache *regcache, int regno) tid = GET_THREAD_ID (inferior_ptid); /* Read the floating point state. */ - ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + struct iovec iov; + + iov.iov_base = &fp; + iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; + + ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to fetch the floating point registers.")); @@ -168,7 +201,18 @@ store_fpregister (const struct regcache *regcache, int regno) if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) collect_nwfpe_register (regcache, regno, fp); - ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + struct iovec iov; + + iov.iov_base = &fp; + iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; + + ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to store floating point register.")); @@ -189,7 +233,19 @@ store_fpregs (const struct regcache *regcache) tid = GET_THREAD_ID (inferior_ptid); /* Read the floating point state. */ - ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + elf_fpregset_t fpregs; + struct iovec iov; + + iov.iov_base = &fpregs; + iov.iov_len = sizeof (fpregs); + + ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PT_GETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to fetch the floating point registers.")); @@ -205,7 +261,18 @@ store_fpregs (const struct regcache *regcache) if (REG_VALID == regcache_register_status (regcache, regno)) collect_nwfpe_register (regcache, regno, fp); - ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); + if (have_ptrace_getregset == 1) + { + struct iovec iov; + + iov.iov_base = &fp; + iov.iov_len = ARM_LINUX_SIZEOF_NWFPE; + + ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iov); + } + else + ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); + if (ret < 0) { warning (_("Unable to store floating point registers."));