From patchwork Tue Mar 31 06:02:10 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Frysinger X-Patchwork-Id: 5920 Received: (qmail 81847 invoked by alias); 31 Mar 2015 06:02:13 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 81837 invoked by uid 89); 31 Mar 2015 06:02:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS, T_RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: smtp.gentoo.org Received: from smtp.gentoo.org (HELO smtp.gentoo.org) (140.211.166.183) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Tue, 31 Mar 2015 06:02:11 +0000 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.gentoo.org (Postfix) with ESMTP id C817634086E for ; Tue, 31 Mar 2015 06:02:09 +0000 (UTC) From: Mike Frysinger To: gdb-patches@sourceware.org Subject: [PATCH] sim: m68hc11: fix gcc-5 build error w/restrict keyword Date: Tue, 31 Mar 2015 02:02:10 -0400 Message-Id: <1427781730-27637-1-git-send-email-vapier@gentoo.org> X-IsSubscribed: yes Committed. --- sim/m68hc11/ChangeLog | 7 +++++++ sim/m68hc11/m68hc11_sim.c | 14 +++++++------- sim/m68hc11/sim-main.h | 2 +- 3 files changed, 15 insertions(+), 8 deletions(-) diff --git a/sim/m68hc11/ChangeLog b/sim/m68hc11/ChangeLog index db46251..b06c3e3 100644 --- a/sim/m68hc11/ChangeLog +++ b/sim/m68hc11/ChangeLog @@ -1,3 +1,10 @@ +2015-03-31 Mike Frysinger + + * m68hc11_sim.c (cpu_get_indexed_operand_addr, + cpu_get_indexed_operand8, cpu_get_indexed_operand16): Rename restrict + variable to restricted. + * sim-main.h (cpu_get_indexed_operand_addr): Likewise. + 2015-03-24 Mike Frysinger * interp.c (sim_pc_get): New function. diff --git a/sim/m68hc11/m68hc11_sim.c b/sim/m68hc11/m68hc11_sim.c index f7c4219d..8a04648 100644 --- a/sim/m68hc11/m68hc11_sim.c +++ b/sim/m68hc11/m68hc11_sim.c @@ -240,7 +240,7 @@ cpu_set_reg (sim_cpu* cpu, uint8 reg, uint16 val) /* Returns the address of a 68HC12 indexed operand. Pre and post modifications are handled on the source register. */ uint16 -cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict) +cpu_get_indexed_operand_addr (sim_cpu* cpu, int restricted) { uint8 reg; uint16 sval; @@ -285,7 +285,7 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict) /* [n,r] 16-bits offset indexed indirect. */ else if ((code & 0x07) == 3) { - if (restrict) + if (restricted) { return 0; } @@ -297,7 +297,7 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict) } else if ((code & 0x4) == 0) { - if (restrict) + if (restricted) { return 0; } @@ -345,20 +345,20 @@ cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict) } uint8 -cpu_get_indexed_operand8 (sim_cpu* cpu, int restrict) +cpu_get_indexed_operand8 (sim_cpu* cpu, int restricted) { uint16 addr; - addr = cpu_get_indexed_operand_addr (cpu, restrict); + addr = cpu_get_indexed_operand_addr (cpu, restricted); return memory_read8 (cpu, addr); } uint16 -cpu_get_indexed_operand16 (sim_cpu* cpu, int restrict) +cpu_get_indexed_operand16 (sim_cpu* cpu, int restricted) { uint16 addr; - addr = cpu_get_indexed_operand_addr (cpu, restrict); + addr = cpu_get_indexed_operand_addr (cpu, restricted); return memory_read16 (cpu, addr); } diff --git a/sim/m68hc11/sim-main.h b/sim/m68hc11/sim-main.h index 5dfc1bf..3973159 100644 --- a/sim/m68hc11/sim-main.h +++ b/sim/m68hc11/sim-main.h @@ -551,7 +551,7 @@ extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu); /* Returns the address of a 68HC12 indexed operand. Pre and post modifications are handled on the source register. */ -extern uint16 cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict); +extern uint16 cpu_get_indexed_operand_addr (sim_cpu *cpu, int restricted); extern void cpu_return (sim_cpu *cpu); extern void cpu_set_sp (sim_cpu *cpu, uint16 val);