From patchwork Fri Sep 5 19:58:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Edjunior Barbosa Machado X-Patchwork-Id: 2659 Received: (qmail 13326 invoked by alias); 5 Sep 2014 20:00:16 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 13268 invoked by uid 89); 5 Sep 2014 20:00:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.1 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: e24smtp01.br.ibm.com Received: from e24smtp01.br.ibm.com (HELO e24smtp01.br.ibm.com) (32.104.18.85) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-SHA encrypted) ESMTPS; Fri, 05 Sep 2014 20:00:08 +0000 Received: from /spool/local by e24smtp01.br.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 5 Sep 2014 16:59:58 -0300 Received: from d24relay01.br.ibm.com (d24relay01.br.ibm.com [9.8.31.16]) by d24dlp01.br.ibm.com (Postfix) with ESMTP id 8C653352004D for ; Fri, 5 Sep 2014 15:59:50 -0400 (EDT) Received: from d24av02.br.ibm.com (d24av02.br.ibm.com [9.8.31.93]) by d24relay01.br.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s85K0KOs4473016 for ; Fri, 5 Sep 2014 17:00:20 -0300 Received: from d24av02.br.ibm.com (localhost [127.0.0.1]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s85JxuJi019510 for ; Fri, 5 Sep 2014 16:59:57 -0300 Received: from grandaddy.ibm.com ([9.78.142.5]) by d24av02.br.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id s85JxtM8019466; Fri, 5 Sep 2014 16:59:56 -0300 From: Edjunior Barbosa Machado To: gdb-patches@sourceware.org Cc: Ulrich Weigand Subject: [PATCH] ppc64le/gdbserver: Fix ppc_collect/supply_ptrace_register() routines Date: Fri, 5 Sep 2014 16:58:22 -0300 Message-Id: <1409947102-32166-1-git-send-email-emachado@linux.vnet.ibm.com> X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 14090519-1524-0000-0000-0000006A5B62 X-IsSubscribed: yes Hi, this patch fixes the routines to collect and supply ptrace registers on ppc64le gdbserver. Originally written for big endian arch, they were causing several issues on little endian. With this fix, the number of unexpected failures in the testsuite dropped from 263 to 72 on ppc64le. Tested on ppc64{,le}. Ok? Thanks and regards, --- Edjunior gdb/gdbserver/ 2014-09-05 Edjunior Barbosa Machado * linux-ppc-low.c (ppc_collect_ptrace_register): Adjust routine to take endianness into account. (ppc_supply_ptrace_register): Likewise. --- gdb/gdbserver/linux-ppc-low.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/gdb/gdbserver/linux-ppc-low.c b/gdb/gdbserver/linux-ppc-low.c index d743311..1898741 100644 --- a/gdb/gdbserver/linux-ppc-low.c +++ b/gdb/gdbserver/linux-ppc-low.c @@ -202,25 +202,44 @@ ppc_cannot_fetch_register (int regno) static void ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf) { - int size = register_size (regcache->tdesc, regno); - memset (buf, 0, sizeof (long)); - if (size < sizeof (long)) - collect_register (regcache, regno, buf + sizeof (long) - size); + if (__BYTE_ORDER == __LITTLE_ENDIAN) + { + /* Little-endian values always sit at the left end of the buffer. */ + collect_register (regcache, regno, buf); + } + else if (__BYTE_ORDER == __BIG_ENDIAN) + { + /* Big-endian values sit at the right end of the buffer. In case of + registers whose size is smaller than sizeof (long), we must use a + padding to access it correctly. */ + int padding = (sizeof (long) - register_size (regcache->tdesc, regno)); + collect_register (regcache, regno, buf + padding); + } else - collect_register (regcache, regno, buf); + perror_with_name ("Unexpected byte order"); } static void ppc_supply_ptrace_register (struct regcache *regcache, int regno, const char *buf) { - int size = register_size (regcache->tdesc, regno); - if (size < sizeof (long)) - supply_register (regcache, regno, buf + sizeof (long) - size); + if (__BYTE_ORDER == __LITTLE_ENDIAN) + { + /* Little-endian values always sit at the left end of the buffer. */ + supply_register (regcache, regno, buf); + } + else if (__BYTE_ORDER == __BIG_ENDIAN) + { + /* Big-endian values sit at the right end of the buffer. In case of + registers whose size is smaller than sizeof (long), we must use a + padding to access it correctly. */ + int padding = (sizeof (long) - register_size (regcache->tdesc, regno)); + supply_register (regcache, regno, buf + padding); + } else - supply_register (regcache, regno, buf); + perror_with_name ("Unexpected byte order"); }