From patchwork Tue May 6 08:21:12 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hui Zhu X-Patchwork-Id: 815 Return-Path: X-Original-To: siddhesh@wilcox.dreamhost.com Delivered-To: siddhesh@wilcox.dreamhost.com Received: from homiemail-mx22.g.dreamhost.com (mx2.sub5.homie.mail.dreamhost.com [208.113.200.128]) by wilcox.dreamhost.com (Postfix) with ESMTP id 86E9B3600BE for ; Tue, 6 May 2014 01:21:24 -0700 (PDT) Received: by homiemail-mx22.g.dreamhost.com (Postfix, from userid 14314964) id 42D7E5359213; Tue, 6 May 2014 01:21:24 -0700 (PDT) X-Original-To: gdb@patchwork.siddhesh.in Delivered-To: x14314964@homiemail-mx22.g.dreamhost.com Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by homiemail-mx22.g.dreamhost.com (Postfix) with ESMTPS id F14FA533D3B7 for ; Tue, 6 May 2014 01:21:23 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:mime-version:content-type :message-id:date; q=dns; s=default; b=uhRnsxP1ICxz/1Eof7sHPNd5sK 2hDH83F08sVv5fGbLFNUu5l+zQJY62MvLMlhWfQH443gT3UqyV3bnc1F3/ILRhKI fBGvFMqBrqnWLKXz7dPcuvW07STdkVisDWpWRoG9hpGWCHOntyG0kLn8hPLIimx+ pk9E3Dx64GldN8PRA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:mime-version:content-type :message-id:date; s=default; bh=Y00AQXpi2CvjHEceLx1Llx1v7QU=; b= tj67OP0Rl7G2K8nNPAm0pDiNHCkveE4mbjhLz0eLw4IWDeyCWvrQDRksITBo2d5b PVM/T7pVnIMmmH4mIr4XjgndJDTOozlnRJKjMOBBW/tzwgl8/E5juyObt+qkOu3O ozdUlw2URbALcp0rJPCN6jRHdzZ4iZpf+O8t8hlvfSo= Received: (qmail 17186 invoked by alias); 6 May 2014 08:21:22 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 17171 invoked by uid 89); 6 May 2014 08:21:20 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00 autolearn=ham version=3.3.2 X-HELO: relay1.mentorg.com Received: from relay1.mentorg.com (HELO relay1.mentorg.com) (192.94.38.131) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 May 2014 08:21:19 +0000 Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1Whacj-0006p8-J2 from Hui_Zhu@mentor.com ; Tue, 06 May 2014 01:21:13 -0700 Received: from SVR-ORW-FEM-02.mgc.mentorg.com ([147.34.96.206]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Tue, 6 May 2014 01:21:13 -0700 Received: from localhost (147.34.91.1) by svr-orw-fem-02.mgc.mentorg.com (147.34.96.168) with Microsoft SMTP Server id 14.2.247.3; Tue, 6 May 2014 01:21:12 -0700 From: Hui Zhu To: Mark Kettenis , Pedro Alves CC: Hui Zhu , H.Peter Anvin , gdb-patches ml Subject: [PATCH v2] Fix interrupt.exp fails with m32 in x86_64 MIME-Version: 1.0 Message-ID: <0a87ce80-983c-4a0e-a5be-f931581873e8@SVR-ORW-FEM-02.mgc.mentorg.com> Date: Tue, 6 May 2014 01:21:12 -0700 X-IsSubscribed: yes X-DH-Original-To: gdb@patchwork.siddhesh.in According to your comments in the discussion thread about Linux kernel patch. I make a new patch for GDB that let %eax sign-extend if %orig_eax >= 0. Thanks, Hui 2014-05-06 Hui Zhu * amd64-linux-nat.c (fill_gregset): Make %eax sign-extended if need. (amd64_linux_store_inferior_registers): Change amd64_collect_native_gregset to fill_gregset. * amd64-nat.c (amd64_native_gregset_reg_offset): Remove static. * amd64-nat.h (amd64_native_gregset_reg_offset): Add extern. --- a/gdb/amd64-linux-nat.c +++ b/gdb/amd64-linux-nat.c @@ -128,7 +128,52 @@ void fill_gregset (const struct regcache *regcache, elf_gregset_t *gregsetp, int regnum) { + struct gdbarch *gdbarch = get_regcache_arch (regcache); + amd64_collect_native_gregset (regcache, gregsetp, regnum); + + /* If target arch is 32 bits and GDB interrupt a system call of + inferior (%orig_rax >= 0), %rax is the errno of this system call. + amd64_collect_native_gregset let %eax zero-extend put %rax from + negative to positive. + If Linux cannot convert value of %rax back, the system call of + inferior will got errno -ERESTARTNOHAND, -ERESTARTSYS, -ERESTARTNOINTR + or -ERESTART_RESTARTBLOCK. + So if this is a 32 bits system call and fill value to %orig_eax + (not %eax to make sure REGCACHE has the right value of %orig_rax) + or all registers, let %eax sign-extend. */ + if (regcache_register_status (regcache, I386_LINUX_ORIG_EAX_REGNUM) + == REG_VALID + && regcache_register_status (regcache, I386_EAX_REGNUM) == REG_VALID + && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32 + && (regnum == I386_LINUX_ORIG_EAX_REGNUM || regnum == -1)) + { + LONGEST val; + gdb_byte buf[MAX_REGISTER_SIZE]; + int orig_eax_size; + + /* Get value of orig_eax and put it to val. */ + regcache_raw_collect (regcache, I386_LINUX_ORIG_EAX_REGNUM, + buf); + orig_eax_size = register_size (gdbarch, + I386_LINUX_ORIG_EAX_REGNUM); + val = extract_signed_integer (buf, orig_eax_size, + gdbarch_byte_order (gdbarch)); + if (val >= 0) + { + /* Make %eax get sign-extended to 64 bits. */ + char *regs = (char *) gregsetp; + int offset = amd64_native_gregset_reg_offset (gdbarch, + I386_EAX_REGNUM); + + regcache_raw_collect (regcache, I386_EAX_REGNUM, + regs + offset); + val = extract_signed_integer ((gdb_byte *)(regs + offset), 4, + gdbarch_byte_order (gdbarch)); + store_signed_integer ((gdb_byte *)(regs + offset), 8, + gdbarch_byte_order (gdbarch), val); + } + } } /* Transfering floating-point registers between GDB, inferiors and cores. */ @@ -234,7 +279,7 @@ amd64_linux_store_inferior_registers (st if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) perror_with_name (_("Couldn't get registers")); - amd64_collect_native_gregset (regcache, ®s, regnum); + fill_gregset (regcache, ®s, regnum); if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) perror_with_name (_("Couldn't write registers")); --- a/gdb/amd64-nat.c +++ b/gdb/amd64-nat.c @@ -51,7 +51,7 @@ int amd64_native_gregset64_num_regs = AM /* Return the offset of REGNUM within the appropriate native general-purpose register set. */ -static int +int amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, int regnum) { int *reg_offset = amd64_native_gregset64_reg_offset; --- a/gdb/amd64-nat.h +++ b/gdb/amd64-nat.h @@ -30,6 +30,12 @@ extern int amd64_native_gregset32_num_re extern int *amd64_native_gregset64_reg_offset; extern int amd64_native_gregset64_num_regs; +/* Return the offset of REGNUM within the appropriate native + general-purpose register set. */ + +extern int amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, + int regnum); + /* Return whether the native general-purpose register set supplies register REGNUM. */