From patchwork Mon Feb 29 23:19:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Evans X-Patchwork-Id: 11150 Received: (qmail 2661 invoked by alias); 29 Feb 2016 23:19:06 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 2649 invoked by uid 89); 29 Feb 2016 23:19:05 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=677, nrw, Hx-languages-length:3062, 507 X-HELO: mail-pa0-f73.google.com Received: from mail-pa0-f73.google.com (HELO mail-pa0-f73.google.com) (209.85.220.73) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Mon, 29 Feb 2016 23:19:04 +0000 Received: by mail-pa0-f73.google.com with SMTP id hj7so9497010pac.0 for ; Mon, 29 Feb 2016 15:19:03 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:message-id:date:subject:from:to:cc; bh=CA9L9Vwfe0SmSKAwt40EzbBzgl0tWTrVjfyMYNBzIlo=; b=Y4yGBYac0v/jrR0HKfbOlWjjHQfnSOIGUiX8B0YZT/+4X6tujpUblh40ja+0TrodxQ MSaGxUzcydBzHAHRoyUrEGaOosiSfC7aumDtFZNfZA0CIhF9+jPeNWrsuQugBJPixBHV DtanU2nt90F7zh37kPMjT48OjqkgVf8qjIdv+wu1iLaDqJdkyR77mxmTbQUlOV4awRbr wVADpyEVf3o0Pc4OSCBYYb66NJoVfZEuXACoMfRAWnDESF6CZUTXjkINprN3Jai6KbWR cBGiGJyf8hC7gJWPE4rACA1pgiCplNZKueZ9JJ2ccbTuhj2Lv9qQh8HcpcJ7NmS2F2a2 S2bA== X-Gm-Message-State: AD7BkJLEKw43BRA7XVZqyPxnSvgoMT9iyW0aCsSACaY1u6V/TPMP/o3FqmAs5PNgYBa5DunhfTACesCPEqPnDw+A7gJ8JbrVWP/KKpMJoblblR/Tc+MW2akXTWCR2JK828UzsUEARANSp4LJTiT8lV+GozE7M6FCWBg+ro8rXE0tEmek7Yc4jg== MIME-Version: 1.0 X-Received: by 10.66.236.129 with SMTP id uu1mr14675626pac.18.1456787942352; Mon, 29 Feb 2016 15:19:02 -0800 (PST) Message-ID: <001a1137efd0d18af3052cf0df46@google.com> Date: Mon, 29 Feb 2016 23:19:02 +0000 Subject: [PATCH 5/5]: Enhancements to "flags": add cpsr_flags to aarch64 From: Doug Evans To: gdb-patches@sourceware.org Cc: cole945@gmail.com X-IsSubscribed: yes Hi. This patch adds a definition for aarch64's cpsr. This register has a two-bit bitfield: EL (which is what started all of this). I didn't do arm32 because I don't have at immediate hand the spec. 2016-02-29 Doug Evans * features/aarch64-core.xml (cpsr_flags): New flags type. (cpsr): Use it. * features/aarch64.c: Regenerate. diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml index b5944fc..8f96296 100644 --- a/gdb/features/aarch64-core.xml +++ b/gdb/features/aarch64-core.xml @@ -42,5 +42,26 @@ - + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/features/aarch64.c b/gdb/features/aarch64.c index 1e9a99d..cec6956 100644 --- a/gdb/features/aarch64.c +++ b/gdb/features/aarch64.c @@ -17,6 +17,23 @@ initialize_tdesc_aarch64 (void) set_tdesc_architecture (result, bfd_scan_arch ("aarch64")); feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.core"); + type = tdesc_create_flags (feature, "cpsr_flags", 4); + tdesc_add_flag (type, 0, "SP"); + tdesc_add_bitfield (type, "", 1, 1); + tdesc_add_bitfield (type, "EL", 2, 3); + tdesc_add_flag (type, 4, "nRW"); + tdesc_add_bitfield (type, "", 5, 5); + tdesc_add_flag (type, 6, "F"); + tdesc_add_flag (type, 7, "I"); + tdesc_add_flag (type, 8, "A"); + tdesc_add_flag (type, 9, "D"); + tdesc_add_flag (type, 20, "IL"); + tdesc_add_flag (type, 21, "SS"); + tdesc_add_flag (type, 28, "V"); + tdesc_add_flag (type, 29, "C"); + tdesc_add_flag (type, 30, "Z"); + tdesc_add_flag (type, 31, "N"); + tdesc_create_reg (feature, "x0", 0, 1, NULL, 64, "int"); tdesc_create_reg (feature, "x1", 1, 1, NULL, 64, "int"); tdesc_create_reg (feature, "x2", 2, 1, NULL, 64, "int"); @@ -50,7 +67,7 @@ initialize_tdesc_aarch64 (void) tdesc_create_reg (feature, "x30", 30, 1, NULL, 64, "int"); tdesc_create_reg (feature, "sp", 31, 1, NULL, 64, "data_ptr"); tdesc_create_reg (feature, "pc", 32, 1, NULL, 64, "code_ptr"); - tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "int"); + tdesc_create_reg (feature, "cpsr", 33, 1, NULL, 32, "cpsr_flags"); feature = tdesc_create_feature (result, "org.gnu.gdb.aarch64.fpu"); field_type = tdesc_named_type (feature, "ieee_double");