From patchwork Wed Oct 1 16:10:47 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Muller X-Patchwork-Id: 3056 Received: (qmail 2262 invoked by alias); 1 Oct 2014 16:10:56 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 2252 invoked by uid 89); 1 Oct 2014 16:10:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.4 required=5.0 tests=AWL, BAYES_50, MSGID_MULTIPLE_AT autolearn=no version=3.3.2 X-HELO: mailhost.u-strasbg.fr Received: from mailhost.u-strasbg.fr (HELO mailhost.u-strasbg.fr) (130.79.222.215) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 01 Oct 2014 16:10:53 +0000 Received: from mailhost.u-strasbg.fr (localhost [127.0.0.1]) by antispam (Postfix) with ESMTP id 9C5A3A0E2E for ; Wed, 1 Oct 2014 18:10:50 +0200 (CEST) Received: from mailhost.u-strasbg.fr (localhost [127.0.0.1]) by antivirus (Postfix) with ESMTP id 8CB22A2174 for ; Wed, 1 Oct 2014 18:10:50 +0200 (CEST) Received: from lmr.u-strasbg.fr (lmr4.u-strasbg.fr [172.30.21.4]) by mr5.u-strasbg.fr (Postfix) with ESMTP id 7B7CDA0E2E for ; Wed, 1 Oct 2014 18:10:49 +0200 (CEST) Received: from lmr.u-strasbg.fr (localhost [127.0.0.1]) by antivirus (Postfix) with ESMTP id 5DB35E9 for ; Wed, 1 Oct 2014 18:10:49 +0200 (CEST) Received: from E6510Muller (gw-ics.u-strasbg.fr [130.79.210.225]) (Authenticated sender: mullerp) by lmr4.u-strasbg.fr (Postfix) with ESMTPSA id 42DC3E8 for ; Wed, 1 Oct 2014 18:10:48 +0200 (CEST) From: "Pierre Muller" To: Subject: [RFA] Fix amd64 dwarf register number mapping Date: Wed, 1 Oct 2014 18:10:47 +0200 Message-ID: <001301cfdd92$43630400$ca290c00$@muller@ics-cnrs.unistra.fr> MIME-Version: 1.0 dwarf register number is defined in "System V Application Binary Interface AMD64 Architecture Processor Supplement Draft Version 0.99.6" The amd64_dwarf_regmap array is missing the 8 MMX registers in Figure 3.36: DWARF Register Number Mapping page 57. This leads to a wrong value for the registers past this point. I don't know if there are already cases where this really fixes a problem, but it is nevertheless a valid correction. Is this OK, or is there a valid reason for this "miss"? Pierre Muller Pascal language maintainer of GDB 2014-10-01 Pierre Muller * amd64-tdep.c (amd64_dwarf_regmap array): Fix amd64 dwarf register numbering, by adding missing MMX registers. diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 7c8575a..b98bc5d 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -201,7 +201,11 @@ static int amd64_dwarf_regmap[] = AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, - /* Control and Status Flags Register. */ + /* MMX Registers 0 - 7. Currently not handled, + see "tdep->num_mmx_regs = 0;" below. */ + -1, -1, -1, -1, -1, -1, -1, -1, + + /* Control and Status Flags Register. */ AMD64_EFLAGS_REGNUM, /* Selector Registers. */