diff mbox series

[pushed,PR114810,LRA] : Recognize alternatives with lack of available registers for insn and demote them.

Message ID 7dd25e5b-b936-4870-adfd-e410d3f535e0@redhat.com
State New
Headers
Series [pushed,PR114810,LRA] : Recognize alternatives with lack of available registers for insn and demote them. |

Checks

Context Check Description
linaro-tcwg-bot/tcwg_gcc_build--master-aarch64 success Testing passed
linaro-tcwg-bot/tcwg_gcc_check--master-aarch64 warning Patch is already merged
linaro-tcwg-bot/tcwg_gcc_build--master-arm warning Patch is already merged

Commit Message

Vladimir Makarov May 8, 2024, 4:40 p.m. UTC 
  The following patch is a fix for PR114810 from LRA side.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

The patch was successfully bootstrapped and tested on x86_64, aarch64, 
ppc64le.

Comments

Li, Pan2 May 9, 2024, 3:25 a.m. UTC | #1 
Hi Vladimir,

Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel free to ping me if more information is needed for reproducing.

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ |     gfortran |
    rv64gcv/  lp64d/ medlow | 1061 /    69 |    0 /     0 |      - |
make: *** [Makefile:1096: report-gcc-newlib] Error 1

Just pick one imm_loop_invariant-10.c as below.

/home/pli/gcc/111/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: error: unrecognizable insn:
(insn 265 0 0 (parallel [
            (set (reg:RVVMF8QI 309 [239])
                (unspec:RVVMF8QI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF))
            (clobber (scratch:SI))
        ]) -1
     (nil))
during RTL pass: reload
…. gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: internal compiler error: in extract_insn, at recog.cc:2812
0xa9d309 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
........../.././gcc/gcc/rtl-error.cc:108
0xa9d32b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
........../.././gcc/gcc/rtl-error.cc:116
0xa9bc07 extract_insn(rtx_insn*)
........../.././gcc/gcc/recog.cc:2812
0x10e5ad2 ira_remove_insn_scratches(rtx_insn*, bool, _IO_FILE*, rtx_def* (*)(rtx_def*))
........../.././gcc/gcc/ira.cc:5381
0x112868f remove_insn_scratches
........../.././gcc/gcc/lra.cc:2154
0x112868f lra_emit_move(rtx_def*, rtx_def*)
........../.././gcc/gcc/lra.cc:513
0x1136883 match_reload
........../.././gcc/gcc/lra-constraints.cc:1184
0x1142ae4 curr_insn_transform
........../.././gcc/gcc/lra-constraints.cc:4778
0x11443cb lra_constraints(bool)
........../.././gcc/gcc/lra-constraints.cc:5481
0x112b192 lra(_IO_FILE*, int)
........../.././gcc/gcc/lra.cc:2442
0x10e0e7f do_reload
........../.././gcc/gcc/ira.cc:5973
0x10e0e7f execute
........../.././gcc/gcc/ira.cc:6161

Pan

From: Vladimir Makarov <vmakarov@redhat.com>
Sent: Thursday, May 9, 2024 12:40 AM
To: gcc-patches@gcc.gnu.org
Subject: [pushed][PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them.


The following patch is a fix for PR114810 from LRA side.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

The patch was successfully bootstrapped and tested on x86_64, aarch64, ppc64le.
Li, Pan2 May 9, 2024, 3:30 a.m. UTC | #2 
CC more RISC-V port people for awareness.

Pan

From: Li, Pan2 <pan2.li@intel.com>
Sent: Thursday, May 9, 2024 11:25 AM
To: Vladimir Makarov <vmakarov@redhat.com>; gcc-patches@gcc.gnu.org
Subject: RE: [pushed][PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them.

Hi Vladimir,

Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel free to ping me if more information is needed for reproducing.

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ |     gfortran |
    rv64gcv/  lp64d/ medlow | 1061 /    69 |    0 /     0 |      - |
make: *** [Makefile:1096: report-gcc-newlib] Error 1

Just pick one imm_loop_invariant-10.c as below.

/home/pli/gcc/111/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: error: unrecognizable insn:
(insn 265 0 0 (parallel [
            (set (reg:RVVMF8QI 309 [239])
                (unspec:RVVMF8QI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF))
            (clobber (scratch:SI))
        ]) -1
     (nil))
during RTL pass: reload
…. gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: internal compiler error: in extract_insn, at recog.cc:2812
0xa9d309 _fatal_insn(char const*, rtx_def const*, char const*, int, char const*)
........../.././gcc/gcc/rtl-error.cc:108
0xa9d32b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
........../.././gcc/gcc/rtl-error.cc:116
0xa9bc07 extract_insn(rtx_insn*)
........../.././gcc/gcc/recog.cc:2812
0x10e5ad2 ira_remove_insn_scratches(rtx_insn*, bool, _IO_FILE*, rtx_def* (*)(rtx_def*))
........../.././gcc/gcc/ira.cc:5381
0x112868f remove_insn_scratches
........../.././gcc/gcc/lra.cc:2154
0x112868f lra_emit_move(rtx_def*, rtx_def*)
........../.././gcc/gcc/lra.cc:513
0x1136883 match_reload
........../.././gcc/gcc/lra-constraints.cc:1184
0x1142ae4 curr_insn_transform
........../.././gcc/gcc/lra-constraints.cc:4778
0x11443cb lra_constraints(bool)
........../.././gcc/gcc/lra-constraints.cc:5481
0x112b192 lra(_IO_FILE*, int)
........../.././gcc/gcc/lra.cc:2442
0x10e0e7f do_reload
........../.././gcc/gcc/ira.cc:5973
0x10e0e7f execute
........../.././gcc/gcc/ira.cc:6161

Pan

From: Vladimir Makarov <vmakarov@redhat.com<mailto:vmakarov@redhat.com>>
Sent: Thursday, May 9, 2024 12:40 AM
To: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>
Subject: [pushed][PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them.


The following patch is a fix for PR114810 from LRA side.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114810

The patch was successfully bootstrapped and tested on x86_64, aarch64, ppc64le.
Vladimir Makarov May 9, 2024, 12:21 p.m. UTC | #3 
On 5/8/24 23:25, Li, Pan2 wrote:
>
> Hi Vladimir,
>
> Looks this patch results in some ICE in the rvv.exp of RISC-V backend, 
> feel free to ping me if more information is needed for reproducing.
>
> ========= Summary of gcc testsuite =========
>
> | # of unexpected case / # of unique unexpected case
>
> |gcc |g++ |gfortran |
>
> rv64gcv/lp64d/ medlow | 1061 /69 |0 /0 |- |
>
> make: *** [Makefile:1096: report-gcc-newlib] Error 1
>
> Just pick one imm_loop_invariant-10.c as below.
>
> /home/pli/gcc/111/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: 
> error: unrecognizable insn:
>
> (insn 265 0 0 (parallel [
>
> (set (reg:RVVMF8QI 309 [239])
>
> (unspec:RVVMF8QI [
>
> (reg:SI 0 zero)
>
> ] UNSPEC_VUNDEF))
>
> (clobber (scratch:SI))
>
> ]) -1
>
> (nil))
>
>
Thank you for reporting this.  Could you fill a PR for this.  I guess 
fixing this might take some time.
Li, Pan2 May 9, 2024, 1:48 p.m. UTC | #4 
Sure thing, see below PR.

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115013

Pan

From: Vladimir Makarov <vmakarov@redhat.com>
Sent: Thursday, May 9, 2024 8:21 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Subject: Re: [pushed][PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them.



On 5/8/24 23:25, Li, Pan2 wrote:
Hi Vladimir,

Looks this patch results in some ICE in the rvv.exp of RISC-V backend, feel free to ping me if more information is needed for reproducing.

               ========= Summary of gcc testsuite =========
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ |     gfortran |
    rv64gcv/  lp64d/ medlow | 1061 /    69 |    0 /     0 |      - |
make: *** [Makefile:1096: report-gcc-newlib] Error 1

Just pick one imm_loop_invariant-10.c as below.

/home/pli/gcc/111/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c:20:1: error: unrecognizable insn:
(insn 265 0 0 (parallel [
            (set (reg:RVVMF8QI 309 [239])
                (unspec:RVVMF8QI [
                        (reg:SI 0 zero)
                    ] UNSPEC_VUNDEF))
            (clobber (scratch:SI))
        ]) -1
     (nil))


Thank you for reporting this.  Could you fill a PR for this.  I guess fixing this might take some time.
diff mbox series

Patch

commit dc859c1fcb6f3ad95022fb078c040907ef361e4c
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Wed May 8 10:39:04 2024 -0400

    [PR114810][LRA]: Recognize alternatives with lack of available registers for insn and demote them.
    
      PR114810 was fixed in machine-dependent way.  This patch is a fix of
    the PR on LRA side.  LRA chose alternative with constraints `&r,r,ro`
    on i686 when all operands of DImode and there are only 6 available
    general regs.  The patch recognizes such case and significantly
    increase the alternative cost.  It does not reject alternative
    completely.  So the fix is safe but it might not work for all
    potentially possible cases of registers lack as register classes can
    have any relations including subsets and intersections.
    
    gcc/ChangeLog:
    
            PR target/114810
            * lra-constraints.cc (process_alt_operands): Calculate union reg
            class for the alternative, peak matched regs and required reload
            regs.  Recognize alternatives with lack of available registers and
            make them costly.  Add debug print about this case.

diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 10e3d4e4097..5b78fd0b7e5 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -2127,6 +2127,8 @@  process_alt_operands (int only_alternative)
   /* Numbers of operands which are early clobber registers.  */
   int early_clobbered_nops[MAX_RECOG_OPERANDS];
   enum reg_class curr_alt[MAX_RECOG_OPERANDS];
+  enum reg_class all_this_alternative;
+  int all_used_nregs, all_reload_nregs;
   HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS];
   HARD_REG_SET curr_alt_exclude_start_hard_regs[MAX_RECOG_OPERANDS];
   bool curr_alt_match_win[MAX_RECOG_OPERANDS];
@@ -2229,7 +2231,8 @@  process_alt_operands (int only_alternative)
       curr_alt_out_sp_reload_p = false;
       curr_reuse_alt_p = true;
       curr_alt_class_change_p = false;
-      
+      all_this_alternative = NO_REGS;
+      all_used_nregs = all_reload_nregs = 0;
       for (nop = 0; nop < n_operands; nop++)
 	{
 	  const char *p;
@@ -2660,6 +2663,15 @@  process_alt_operands (int only_alternative)
 	  /* Record which operands fit this alternative.  */
 	  if (win)
 	    {
+	      if (early_clobber_p
+		  || curr_static_id->operand[nop].type != OP_OUT)
+		{
+		  all_used_nregs
+		    += ira_reg_class_min_nregs[this_alternative][mode];
+		  all_this_alternative
+		    = (reg_class_subunion
+		       [all_this_alternative][this_alternative]);
+		}
 	      this_alternative_win = true;
 	      if (class_change_p)
 		{
@@ -2781,7 +2793,19 @@  process_alt_operands (int only_alternative)
 		       & ~((ira_prohibited_class_mode_regs
 			    [this_alternative][mode])
 			   | lra_no_alloc_regs));
-		  if (hard_reg_set_empty_p (available_regs))
+		  if (!hard_reg_set_empty_p (available_regs))
+		    {
+		      if (early_clobber_p
+			  || curr_static_id->operand[nop].type != OP_OUT)
+			{
+			  all_reload_nregs
+			    += ira_reg_class_min_nregs[this_alternative][mode];
+			  all_this_alternative
+			    = (reg_class_subunion
+			       [all_this_alternative][this_alternative]);
+			}
+		    }
+		  else
 		    {
 		      /* There are no hard regs holding a value of given
 			 mode.  */
@@ -3217,6 +3241,21 @@  process_alt_operands (int only_alternative)
 		     "            Cycle danger: overall += LRA_MAX_REJECT\n");
 	  overall += LRA_MAX_REJECT;
 	}
+      if (all_this_alternative != NO_REGS
+	  && all_used_nregs != 0 && all_reload_nregs != 0
+	  && (all_used_nregs + all_reload_nregs + 1
+	      >= ira_class_hard_regs_num[all_this_alternative]))
+	{
+	  if (lra_dump_file != NULL)
+	    fprintf
+	      (lra_dump_file,
+	       "            Register starvation: overall += LRA_MAX_REJECT"
+	       "(class=%s,avail=%d,used=%d,reload=%d)\n",
+	       reg_class_names[all_this_alternative],
+	       ira_class_hard_regs_num[all_this_alternative],
+	       all_used_nregs, all_reload_nregs);
+	  overall += LRA_MAX_REJECT;
+	}
       ok_p = true;
       curr_alt_dont_inherit_ops_num = 0;
       for (nop = 0; nop < early_clobbered_regs_num; nop++)