diff mbox

[v2,7/6,powerpc] Rename fesetenv_mode to fesetenv_control

Message ID 1568920496-26685-1-git-send-email-pc@us.ibm.com
State Committed
Headers

Commit Message

Paul A. Clarke Sept. 19, 2019, 7:14 p.m. UTC 
  From: "Paul A. Clarke" <pc@us.ibm.com>

fesetenv_mode is used variously to write the FPSCR exception enable
bits and rounding mode bits.  These are referred to as the control
bits in the POWER ISA.  Change the name to be reflective of its
current and expected use, and match up well with fegetenv_control.

2019-09-19  Paul A. Clarke  <pc@us.ibm.com>

	* sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to
	fesetenv_control.
	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
	rename of fesetenv_mode to fegetenv_control.
	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
	* sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise.
	(libc_feholdsetround_noex_ppc_ctx): Likewise.
---
This patch should've been tacked onto the series that I just posted
"[PATCH v2 0/6] Various FPSCR-related changes", thus the "7/6".  :-?
This is a new patch.

 sysdeps/powerpc/fpu/fedisblxcpt.c  | 2 +-
 sysdeps/powerpc/fpu/feenablxcpt.c  | 2 +-
 sysdeps/powerpc/fpu/fenv_libc.h    | 2 +-
 sysdeps/powerpc/fpu/fenv_private.h | 4 ++--
 sysdeps/powerpc/fpu/fesetmode.c    | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

Comments

Paul E Murphy Sept. 23, 2019, 4:24 p.m. UTC | #1 
On 9/19/19 2:14 PM, Paul A. Clarke wrote:
> From: "Paul A. Clarke" <pc@us.ibm.com>
> 
> fesetenv_mode is used variously to write the FPSCR exception enable
> bits and rounding mode bits.  These are referred to as the control
> bits in the POWER ISA.  Change the name to be reflective of its
> current and expected use, and match up well with fegetenv_control.
> 
> 2019-09-19  Paul A. Clarke  <pc@us.ibm.com>
> 
> 	* sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to
> 	fesetenv_control.
> 	* sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate
> 	rename of fesetenv_mode to fegetenv_control.
> 	* sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise.
> 	* sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise.
> 	* sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise.
> 	(libc_feholdsetround_noex_ppc_ctx): Likewise.
> ---
> This patch should've been tacked onto the series that I just posted
> "[PATCH v2 0/6] Various FPSCR-related changes", thus the "7/6".  :-?
> This is a new patch
OK.

Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
diff mbox

Patch

diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c
index 870cfc8..9f86c5f 100644
--- a/sysdeps/powerpc/fpu/fedisblxcpt.c
+++ b/sysdeps/powerpc/fpu/fedisblxcpt.c
@@ -41,7 +41,7 @@  fedisableexcept (int excepts)
   fe.l &= ~new;
 
   if (fe.l != curr.l)
-    fesetenv_mode (fe.fenv);
+    fesetenv_control (fe.fenv);
 
   __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l);
 
diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c
index 43f6482..141cfb4 100644
--- a/sysdeps/powerpc/fpu/feenablxcpt.c
+++ b/sysdeps/powerpc/fpu/feenablxcpt.c
@@ -41,7 +41,7 @@  feenableexcept (int excepts)
   fe.l |= new;
 
   if (fe.l != curr.l)
-    fesetenv_mode (fe.fenv);
+    fesetenv_control (fe.fenv);
 
   __TEST_AND_EXIT_NON_STOP (0ULL, fe.l);
 
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
index 231d264..ed6cfeb 100644
--- a/sysdeps/powerpc/fpu/fenv_libc.h
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -124,7 +124,7 @@  extern const fenv_t *__fe_mask_env (void) attribute_hidden;
 /* Set the last 2 nibbles of the FPSCR, which contain the
    exception enables and the rounding mode.
    'fegetenv_control' retrieves these bits by reading the FPSCR.  */
-#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env));
+#define fesetenv_control(env) __builtin_mtfsf (0b00000011, (env));
 
 /* This very handy macro:
    - Sets the rounding mode to 'round to nearest';
diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h
index ade0bfa..5eedc3b 100644
--- a/sysdeps/powerpc/fpu/fenv_private.h
+++ b/sysdeps/powerpc/fpu/fenv_private.h
@@ -61,7 +61,7 @@  __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask,
       == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) &&
       (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK))
   {
-    fesetenv_mode (new.fenv);
+    fesetenv_control (new.fenv);
   }
   else
     /* Atomically enable and raise (if appropriate) exceptions set in `new'.  */
@@ -142,7 +142,7 @@  libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r)
   if (__glibc_unlikely (new.l != old.l))
     {
       __TEST_AND_ENTER_NON_STOP (old.l, 0ULL);
-      fesetenv_mode (new.fenv);
+      fesetenv_control (new.fenv);
       ctx->updated_status = true;
     }
   else
diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c
index 1e9a874..a7ead9f 100644
--- a/sysdeps/powerpc/fpu/fesetmode.c
+++ b/sysdeps/powerpc/fpu/fesetmode.c
@@ -36,6 +36,6 @@  fesetmode (const femode_t *modep)
   __TEST_AND_EXIT_NON_STOP (old.l, new.l);
   __TEST_AND_ENTER_NON_STOP (old.l, new.l);
 
-  fesetenv_mode (new.fenv);
+  fesetenv_control (new.fenv);
   return 0;
 }