[v2] AArch64: Add missing CPSR flags
Commit Message
[ This update does not add the 8.5 BTI bitfield. There is no support
yet in Linux for it. By defining it now, because it's a bitfield
it would always be shown in CPSR, which would be confusing. I will
return to BTI once Linux support for it is in. ]
Add all the CPSR flags for Armv8.1-A through to Armv8.4-A.
In addition, document all the existing flags, and remove
the superfluous empty spaces.
gdb/ChangeLog:
2019-06-11 Alan Hayward <alan.hayward@arm.com>
* features/aarch64-core.c (create_feature_aarch64_core):
Regenerate.
* features/aarch64-core.xml: Add cpsr flags.
---
gdb/features/aarch64-core.c | 7 +++++--
gdb/features/aarch64-core.xml | 28 ++++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 4 deletions(-)
--
2.20.1 (Apple Git-117)
Comments
I pushed this too.
> On 11 Jun 2019, at 10:23, Alan Hayward <Alan.Hayward@arm.com> wrote:
>
> [ This update does not add the 8.5 BTI bitfield. There is no support
> yet in Linux for it. By defining it now, because it's a bitfield
> it would always be shown in CPSR, which would be confusing. I will
> return to BTI once Linux support for it is in. ]
>
> Add all the CPSR flags for Armv8.1-A through to Armv8.4-A.
>
> In addition, document all the existing flags, and remove
> the superfluous empty spaces.
>
> gdb/ChangeLog:
>
> 2019-06-11 Alan Hayward <alan.hayward@arm.com>
>
> * features/aarch64-core.c (create_feature_aarch64_core):
> Regenerate.
> * features/aarch64-core.xml: Add cpsr flags.
> ---
> gdb/features/aarch64-core.c | 7 +++++--
> gdb/features/aarch64-core.xml | 28 ++++++++++++++++++++++++++--
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c
> index cd3de02cbc..c6e1910be0 100644
> --- a/gdb/features/aarch64-core.c
> +++ b/gdb/features/aarch64-core.c
> @@ -12,16 +12,19 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
> tdesc_type_with_fields *type_with_fields;
> type_with_fields = tdesc_create_flags (feature, "cpsr_flags", 4);
> tdesc_add_flag (type_with_fields, 0, "SP");
> - tdesc_add_flag (type_with_fields, 1, "");
> tdesc_add_bitfield (type_with_fields, "EL", 2, 3);
> tdesc_add_flag (type_with_fields, 4, "nRW");
> - tdesc_add_flag (type_with_fields, 5, "");
> tdesc_add_flag (type_with_fields, 6, "F");
> tdesc_add_flag (type_with_fields, 7, "I");
> tdesc_add_flag (type_with_fields, 8, "A");
> tdesc_add_flag (type_with_fields, 9, "D");
> + tdesc_add_flag (type_with_fields, 12, "SSBS");
> tdesc_add_flag (type_with_fields, 20, "IL");
> tdesc_add_flag (type_with_fields, 21, "SS");
> + tdesc_add_flag (type_with_fields, 22, "PAN");
> + tdesc_add_flag (type_with_fields, 23, "UAO");
> + tdesc_add_flag (type_with_fields, 24, "DIT");
> + tdesc_add_flag (type_with_fields, 25, "TCO");
> tdesc_add_flag (type_with_fields, 28, "V");
> tdesc_add_flag (type_with_fields, 29, "C");
> tdesc_add_flag (type_with_fields, 30, "Z");
> diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
> index 6c6b98552b..3687981589 100644
> --- a/gdb/features/aarch64-core.xml
> +++ b/gdb/features/aarch64-core.xml
> @@ -44,22 +44,46 @@
> <reg name="pc" bitsize="64" type="code_ptr"/>
>
> <flags id="cpsr_flags" size="4">
> + <!-- Stack Pointer. -->
> <field name="SP" start="0" end="0"/>
> - <field name="" start="1" end="1"/>
> +
> + <!-- Exception Level. -->
> <field name="EL" start="2" end="3"/>
> + <!-- Execution state. -->
> <field name="nRW" start="4" end="4"/>
> - <field name="" start="5" end="5"/>
> +
> + <!-- FIQ interrupt mask. -->
> <field name="F" start="6" end="6"/>
> + <!-- IRQ interrupt mask. -->
> <field name="I" start="7" end="7"/>
> + <!-- SError interrupt mask. -->
> <field name="A" start="8" end="8"/>
> + <!-- Debug exception mask. -->
> <field name="D" start="9" end="9"/>
>
> + <!-- ARMv8.0-A: Speculative Store Bypass. -->
> + <field name="SSBS" start="12" end="12"/>
> +
> + <!-- Illegal Execution state. -->
> <field name="IL" start="20" end="20"/>
> + <!-- Software Step. -->
> <field name="SS" start="21" end="21"/>
> + <!-- ARMv8.1-A: Privileged Access Never. -->
> + <field name="PAN" start="22" end="22"/>
> + <!-- ARMv8.2-A: User Access Override. -->
> + <field name="UAO" start="23" end="23"/>
> + <!-- ARMv8.4-A: Data Independent Timing. -->
> + <field name="DIT" start="24" end="24"/>
> + <!-- ARMv8.5-A: Tag Check Override. -->
> + <field name="TCO" start="25" end="25"/>
>
> + <!-- Overflow Condition flag. -->
> <field name="V" start="28" end="28"/>
> + <!-- Carry Condition flag. -->
> <field name="C" start="29" end="29"/>
> + <!-- Zero Condition flag. -->
> <field name="Z" start="30" end="30"/>
> + <!-- Negative Condition flag. -->
> <field name="N" start="31" end="31"/>
> </flags>
> <reg name="cpsr" bitsize="32" type="cpsr_flags"/>
> --
> 2.20.1 (Apple Git-117)
>
@@ -12,16 +12,19 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
tdesc_type_with_fields *type_with_fields;
type_with_fields = tdesc_create_flags (feature, "cpsr_flags", 4);
tdesc_add_flag (type_with_fields, 0, "SP");
- tdesc_add_flag (type_with_fields, 1, "");
tdesc_add_bitfield (type_with_fields, "EL", 2, 3);
tdesc_add_flag (type_with_fields, 4, "nRW");
- tdesc_add_flag (type_with_fields, 5, "");
tdesc_add_flag (type_with_fields, 6, "F");
tdesc_add_flag (type_with_fields, 7, "I");
tdesc_add_flag (type_with_fields, 8, "A");
tdesc_add_flag (type_with_fields, 9, "D");
+ tdesc_add_flag (type_with_fields, 12, "SSBS");
tdesc_add_flag (type_with_fields, 20, "IL");
tdesc_add_flag (type_with_fields, 21, "SS");
+ tdesc_add_flag (type_with_fields, 22, "PAN");
+ tdesc_add_flag (type_with_fields, 23, "UAO");
+ tdesc_add_flag (type_with_fields, 24, "DIT");
+ tdesc_add_flag (type_with_fields, 25, "TCO");
tdesc_add_flag (type_with_fields, 28, "V");
tdesc_add_flag (type_with_fields, 29, "C");
tdesc_add_flag (type_with_fields, 30, "Z");
@@ -44,22 +44,46 @@
<reg name="pc" bitsize="64" type="code_ptr"/>
<flags id="cpsr_flags" size="4">
+ <!-- Stack Pointer. -->
<field name="SP" start="0" end="0"/>
- <field name="" start="1" end="1"/>
+
+ <!-- Exception Level. -->
<field name="EL" start="2" end="3"/>
+ <!-- Execution state. -->
<field name="nRW" start="4" end="4"/>
- <field name="" start="5" end="5"/>
+
+ <!-- FIQ interrupt mask. -->
<field name="F" start="6" end="6"/>
+ <!-- IRQ interrupt mask. -->
<field name="I" start="7" end="7"/>
+ <!-- SError interrupt mask. -->
<field name="A" start="8" end="8"/>
+ <!-- Debug exception mask. -->
<field name="D" start="9" end="9"/>
+ <!-- ARMv8.0-A: Speculative Store Bypass. -->
+ <field name="SSBS" start="12" end="12"/>
+
+ <!-- Illegal Execution state. -->
<field name="IL" start="20" end="20"/>
+ <!-- Software Step. -->
<field name="SS" start="21" end="21"/>
+ <!-- ARMv8.1-A: Privileged Access Never. -->
+ <field name="PAN" start="22" end="22"/>
+ <!-- ARMv8.2-A: User Access Override. -->
+ <field name="UAO" start="23" end="23"/>
+ <!-- ARMv8.4-A: Data Independent Timing. -->
+ <field name="DIT" start="24" end="24"/>
+ <!-- ARMv8.5-A: Tag Check Override. -->
+ <field name="TCO" start="25" end="25"/>
+ <!-- Overflow Condition flag. -->
<field name="V" start="28" end="28"/>
+ <!-- Carry Condition flag. -->
<field name="C" start="29" end="29"/>
+ <!-- Zero Condition flag. -->
<field name="Z" start="30" end="30"/>
+ <!-- Negative Condition flag. -->
<field name="N" start="31" end="31"/>
</flags>
<reg name="cpsr" bitsize="32" type="cpsr_flags"/>