From patchwork Mon Oct 1 22:26:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Trent Piepho X-Patchwork-Id: 29609 Received: (qmail 130882 invoked by alias); 1 Oct 2018 22:26:09 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 130610 invoked by uid 89); 1 Oct 2018 22:26:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: NAM02-CY1-obe.outbound.protection.outlook.com Received: from mail-cys01nam02on0105.outbound.protection.outlook.com (HELO NAM02-CY1-obe.outbound.protection.outlook.com) (104.47.37.105) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 01 Oct 2018 22:26:05 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=impinj.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=x79p8aQQigjLpvl1gFRpp1/LonmpIChR7rpk/EmcBos=; b=aPNKQFXRafM1v9fjRh7ROS/jQQFtt5MSPJ5DLSIcrkAC8HwXX/daU5NcnmRloYna9YSU3SueUtgqInvCERDIq5PvjSEHM99H+ELfRjTQmTJe4RJDU777NZqOiZvB2gvm3+NKCpK5iRG6lKdLQb9YSB2cyMpTf3REEmqlr8NQFds= Received: from MWHPR0601MB3708.namprd06.prod.outlook.com (10.167.236.38) by MWHPR0601MB3641.namprd06.prod.outlook.com (10.167.236.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Mon, 1 Oct 2018 22:26:02 +0000 Received: from MWHPR0601MB3708.namprd06.prod.outlook.com ([fe80::f4ee:3633:74c0:ab4]) by MWHPR0601MB3708.namprd06.prod.outlook.com ([fe80::f4ee:3633:74c0:ab4%3]) with mapi id 15.20.1185.024; Mon, 1 Oct 2018 22:26:02 +0000 From: Trent Piepho To: "gdb-patches@sourceware.org" CC: Trent Piepho Subject: [PATCH v3 2/2] Check thumb2 load/store and cache hit addressing mode Date: Mon, 1 Oct 2018 22:26:02 +0000 Message-ID: <20181001222544.4307-2-tpiepho@impinj.com> References: <20181001222544.4307-1-tpiepho@impinj.com> In-Reply-To: <20181001222544.4307-1-tpiepho@impinj.com> received-spf: None (protection.outlook.com: impinj.com does not designate permitted sender hosts) authentication-results: spf=none (sender IP is ) smtp.mailfrom=tpiepho@impinj.com; MIME-Version: 1.0 There are a number of different addressing forms available for these thumb2 instructions. However, not all modes are valid for all instructions, nor is every possible bit pattern a valid mode. PLD/PLI are not that complex so verify that one of the valid modes for those instructions was used. Other instructions are checked for a valid mode encoding, but not necessary that the particular mode is valid for the full instruction. gdb/ChangeLog: 2018-10-01 Trent Piepho * arm-tdep.c (thumb2_ld_mem_hint_mode): Decode addressing mode. (thumb2_record_ld_mem_hints): Check addressing mode. --- Changes from v2: * Fix logic flaw that allowed invalid non PLI/D instructions to be considered PLI/D instructions. gdb/arm-tdep.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 90936ada8e..f7b51d4805 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -12661,6 +12661,51 @@ thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r) return ARM_RECORD_SUCCESS; } + +/* Decode addressing mode of thumb2 load and store single data item, + and memory hints */ + +static int +thumb2_ld_mem_hint_mode (insn_decode_record *thumb2_insn_r) +{ + /* Check Rn = 0b1111 */ + if (bits (thumb2_insn_r->arm_insn, 16, 19) == 0xf) + { + if (bit (thumb2_insn_r->arm_insn, 20) == 1) + return 1; /* PC +/- imm12 */ + else + return -1; /* reserved */ + } + + /* Check U = 1 */ + if (bit (thumb2_insn_r->arm_insn, 23) == 1) + return 2; /* Rn + imm2 */ + + /* Check op2[5] = 0 */ + if (bit (thumb2_insn_r->arm_insn, 11) == 0) + { + if (bits (thumb2_insn_r->arm_insn, 6, 10) == 0) + return 7; /* Rn + shifted register */ + return -1; /* reserved */ + } + + switch (bits (thumb2_insn_r->arm_insn, 8, 10)) + { + case 0x4: + return 3; /* Rn - imm8 */ + case 0x6: + return 4; /* Rn + imm8, User privilege */ + case 0x1: + case 0x3: + return 5; /* Rn post-indexed by +/- imm8 */ + case 0x5: + case 0x7: + return 6; /* Rn pre-indexed by +/- imm8 */ + default: + return -1; /* reserved */ + } +} + /* Handler for thumb2 load memory hints instructions. */ static int @@ -12668,27 +12713,35 @@ thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r) { uint32_t record_buf[8]; uint32_t reg_rt, reg_rn; + uint32_t mode; reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15); reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); + mode = thumb2_ld_mem_hint_mode(thumb2_insn_r); + /* This does not check every possible addressing mode + data size + * combination for validity */ if (ARM_PC_REGNUM != reg_rt) { - record_buf[0] = reg_rt; - record_buf[1] = reg_rn; - record_buf[2] = ARM_PS_REGNUM; - thumb2_insn_r->reg_rec_count = 3; + if (mode != -1) + { + record_buf[0] = reg_rt; + record_buf[1] = reg_rn; + record_buf[2] = ARM_PS_REGNUM; + thumb2_insn_r->reg_rec_count = 3; - REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, - record_buf); - return ARM_RECORD_SUCCESS; + REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, + record_buf); + return ARM_RECORD_SUCCESS; + } } else { if (bits (thumb2_insn_r->arm_insn, 20, 22) == 0x1) { /* Handle PLD, PLI affect only caches, so nothing to record */ - return ARM_RECORD_SUCCESS; + if (mode == 1 || mode == 2 || mode == 3 || mode == 7) + return ARM_RECORD_SUCCESS; } }