Patchwork [v2,2/2] Check thumb2 load/store and cache hit addressing mode

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Submitter Trent Piepho
Date Oct. 1, 2018, 10:08 p.m.
Message ID <20181001220826.10429-2-tpiepho@impinj.com>
Download mbox | patch
Permalink /patch/29607/
State New
Headers show

Comments

Trent Piepho - Oct. 1, 2018, 10:08 p.m.
There are a number of different addressing forms available for these
thumb2 instructions.  However, not all modes are valid for all
instructions, nor is every possible bit pattern a valid mode.

PLD/PLI are not that complex so verify that one of the valid modes for
those instructions was used.

Other instructions are checked for a valid mode encoding, but not
necessary that the particular mode is valid for the full instruction.

gdb/ChangeLog:

2018-10-01  Trent Piepho  <tpiepho@impinj.com>

        * arm-tdep.c (thumb2_ld_mem_hint_mode): Decode addressing mode.
        (thumb2_record_ld_mem_hints): Check addressing mode.
---
 gdb/arm-tdep.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 2 deletions(-)

Patch

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 90936ada8e..2d6c17b5d7 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -12661,6 +12661,51 @@  thumb2_record_str_single_data (insn_decode_record *thumb2_insn_r)
   return ARM_RECORD_SUCCESS;
 }
 
+
+/* Decode addressing mode of thumb2 load and store single data item,
+   and memory hints */
+
+static int
+thumb2_ld_mem_hint_mode (insn_decode_record *thumb2_insn_r)
+{
+  /* Check Rn = 0b1111 */
+  if (bits (thumb2_insn_r->arm_insn, 16, 19) == 0xf)
+    {
+      if (bit (thumb2_insn_r->arm_insn, 20) == 1)
+	return 1; /* PC +/- imm12 */
+      else
+	return -1; /* reserved */
+    }
+
+  /* Check U = 1 */
+  if (bit (thumb2_insn_r->arm_insn, 23) == 1)
+    return 2; /* Rn + imm2 */
+
+  /* Check op2[5] = 0 */
+  if (bit (thumb2_insn_r->arm_insn, 11) == 0)
+    {
+      if (bits (thumb2_insn_r->arm_insn, 6, 10) == 0)
+	return 7; /* Rn + shifted register */
+      return -1; /* reserved */
+    }
+
+  switch (bits (thumb2_insn_r->arm_insn, 8, 10))
+    {
+      case 0x4:
+	return 3; /* Rn - imm8 */
+      case 0x6:
+	return 4; /* Rn + imm8, User privilege */
+      case 0x1:
+      case 0x3:
+	return 5; /* Rn post-indexed by +/- imm8 */
+      case 0x5:
+      case 0x7:
+	return 6; /* Rn pre-indexed by +/- imm8 */
+      default:
+	return -1; /* reserved */
+    }
+}
+
 /* Handler for thumb2 load memory hints instructions.  */
 
 static int
@@ -12668,11 +12713,15 @@  thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
 {
   uint32_t record_buf[8];
   uint32_t reg_rt, reg_rn;
+  uint32_t mode;
 
   reg_rt = bits (thumb2_insn_r->arm_insn, 12, 15);
   reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19);
+  mode = thumb2_ld_mem_hint_mode(thumb2_insn_r);
 
-  if (ARM_PC_REGNUM != reg_rt)
+  /* This does not check every possible addressing mode + data size
+   * combination for validity */
+  if (ARM_PC_REGNUM != reg_rt && mode != -1)
     {
       record_buf[0] = reg_rt;
       record_buf[1] = reg_rn;
@@ -12688,7 +12737,8 @@  thumb2_record_ld_mem_hints (insn_decode_record *thumb2_insn_r)
       if (bits (thumb2_insn_r->arm_insn, 20, 22) == 0x1)
 	{
 	  /* Handle PLD, PLI affect only caches, so nothing to record */
-	  return ARM_RECORD_SUCCESS;
+	  if (mode == 1 || mode == 2 || mode == 3 || mode == 7)
+	    return ARM_RECORD_SUCCESS;
 	}
     }