From patchwork Fri Sep 28 20:41:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Marchi X-Patchwork-Id: 29577 Received: (qmail 24758 invoked by alias); 28 Sep 2018 20:41:51 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 24749 invoked by uid 89); 28 Sep 2018 20:41:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.2 spammy=avx512, gdbpatches, gdb_test, gdb-patches X-HELO: sessmg23.ericsson.net Received: from sessmg23.ericsson.net (HELO sessmg23.ericsson.net) (193.180.251.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 28 Sep 2018 20:41:48 +0000 DKIM-Signature: v=1; a=rsa-sha256; d=ericsson.com; s=mailgw201801; c=relaxed/simple; q=dns/txt; i=@ericsson.com; t=1538167306; h=From:Sender:Reply-To:Subject:Date:Message-ID:To:CC:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=qOQcEIwGiba/VyuJsUOPjTBSyT50stXZiEIJ/18Trzo=; b=et7GVy6sDTzt8m6lNDHoAoB/RgL1uIF1nylox/v5RZ7DbMj4pSFX+QqkpgecG08E HtSkO9hLQXI0Aa3mZlxjbLVQqDhYSPngpeKr4aOHJP8JIJDsUc0uCeCQDvkflCr7 X7+Nee2+ZXMMI83tKS05DsijnZpu34zIRvKOlU4qC1k=; Received: from ESESBMB503.ericsson.se (Unknown_Domain [153.88.183.116]) by sessmg23.ericsson.net (Symantec Mail Security) with SMTP id DC.BD.22015.A029EAB5; Fri, 28 Sep 2018 22:41:46 +0200 (CEST) Received: from ESESBMB503.ericsson.se (153.88.183.170) by ESESBMB503.ericsson.se (153.88.183.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 28 Sep 2018 22:41:45 +0200 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (153.88.183.157) by ESESBMB503.ericsson.se (153.88.183.170) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3 via Frontend Transport; Fri, 28 Sep 2018 22:41:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ericsson.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=m1Riq+HtdhHM/XLTsnmX9EfwB91gT+MUPAV00NF7gwg=; b=OH7M08VJIx1PMlhTVlsxnBcT29mHJKA1ZMjyOlThUy4pN6Gvn5AMfoyB3kM3kYW3DAIKBh5nwOOZqnC17qvLhN9MUhSjLNKfUCP2lw7S3C3Mvb5bfzMcv12aAkpzCa9+vfIzueias/SXsUjuzeeAfwx3N4IFlVW0M0ETkYdOykY= Received: from BYAPR15MB2390.namprd15.prod.outlook.com (52.135.198.30) by BYAPR15MB2455.namprd15.prod.outlook.com (52.135.200.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1185.22; Fri, 28 Sep 2018 20:41:43 +0000 Received: from BYAPR15MB2390.namprd15.prod.outlook.com ([fe80::6d9c:234d:1f2f:cecd]) by BYAPR15MB2390.namprd15.prod.outlook.com ([fe80::6d9c:234d:1f2f:cecd%4]) with mapi id 15.20.1143.019; Fri, 28 Sep 2018 20:41:43 +0000 From: Simon Marchi To: "gdb-patches@sourceware.org" CC: Markus Metzger , Simon Marchi Subject: [PATCH] Fix is_amd64_regs_target check in i386-avx512.exp Date: Fri, 28 Sep 2018 20:41:42 +0000 Message-ID: <20180928204114.20491-1-simon.marchi@ericsson.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=simon.marchi@ericsson.com; received-spf: None (protection.outlook.com: ericsson.com does not designate permitted sender hosts) MIME-Version: 1.0 Return-Path: simon.marchi@ericsson.com X-IsSubscribed: yes As reported by Jan here: https://sourceware.org/ml/gdb-patches/2018-09/msg00831.html the check that sets the number of available registers seems backwards. I can't test this patch however, since I don't have access to a cpu with AVX512. Could somebody perhaps from Intel, or somebody else that has access to such CPU, take a look? Alternatively, do you know if a machine in the GCC compile farm has this feature? I didn't find any, but maybe I didn't look enough. gdb/testsuite/ChangeLog: * gdb.arch/i386-avx512.exp: Fix setting of nr_regs based on is_amd64_regs_target. --- gdb/testsuite/gdb.arch/i386-avx512.exp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdb/testsuite/gdb.arch/i386-avx512.exp b/gdb/testsuite/gdb.arch/i386-avx512.exp index de2f62c3e1f..f27af534cfd 100644 --- a/gdb/testsuite/gdb.arch/i386-avx512.exp +++ b/gdb/testsuite/gdb.arch/i386-avx512.exp @@ -93,9 +93,9 @@ gdb_test "break [gdb_get_line_number "third breakpoint here"]" \ gdb_continue_to_breakpoint "continue to third breakpoint in main" if [is_amd64_regs_target] { - set nr_regs 8 -} else { set nr_regs 32 +} else { + set nr_regs 8 } for { set r 0 } { $r < $nr_regs } { incr r } {